[go: up one dir, main page]

Schmidt et al., 2016 - Google Patents

Advanced Package FA Flow for Next-Gen Packaging Technology Using EOTPR, 3D X-Ray and Plasma FIB

Schmidt et al., 2016

Document ID
16240580225838354992
Author
Schmidt C
Pichumani P
Alton J
Igarashi M
Chan L
Principe E
Publication year
Publication venue
International Symposium for Testing and Failure Analysis

External Links

Snippet

Within this paper, the authors present an adapted FA flow for state-of-the-art Package Failure Analysis for 20nm technology and below. As a key aspect, three methods (EOTPR, 3D Xray & PFIB) are introduced as the next-gen FA standard methods for emerging package …
Continue reading at dl.asminternational.org (other versions)

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • G01R31/2853Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10Measuring as part of the manufacturing process
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06513Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/302Contactless testing
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H01L22/22Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area

Similar Documents

Publication Publication Date Title
Altmann et al. Innovative failure analysis techniques for 3-D packaging developments
Hartfield et al. From PCB to BEOL: 3D X-ray microscopy for advanced semiconductor packaging
De Wolf et al. Expected failures in 3-D technology and related failure analysis challenges
Li et al. A review of failure analysis methods for advanced 3D microelectronic packages
Krause et al. Characterization and failure analysis of TSV interconnects: From non-destructive defect localization to material analysis with nanometer resolution
Barbeau et al. Electro optical terahertz pulse reflectometry—A fast and highly accurate non-destructive fault isolation technique for 3D flip chip packages
Schmidt et al. Advanced Package FA Flow for Next-Gen Packaging Technology Using EOTPR, 3D X-Ray and Plasma FIB
Sekhar et al. Non-destructive testing of a high dense small dimension through silicon via (TSV) array structures by using 3D X-ray computed tomography method (CT scan)
Cao et al. Advanced fault isolation technique using electro-optical terahertz pulse reflectometry (EOTPR) for 2D and 2.5 D flip-chip package
Cason et al. Application of X-ray MicroCT for non-destructive failure analysis and package construction characterization
Gourikutty et al. Non-destructive fault isolation in through-silicon interposer based system in package
Schmidt 3-D X-Ray imaging with nanometer resolution for advanced semiconductor packaging FA
Schmidt et al. Localization of electrical active defects caused by reliability-related failure mechanism by the application of Lock-in Thermography
US6953755B2 (en) Technique for monitoring the state of metal lines in microstructures
Okoro et al. Evaluation of the helium hermeticity reliability of copper through-glass vias
Gaudestad et al. Failure analysis work flow for electrical shorts in triple stacked 3D TSV daisy chains
Altmann et al. Failure analysis strategies for multistacked memory devices with TSV interconnects
Altmann et al. Failure analysis techniques for 3d packages
CN118974574A (en) Method and apparatus for testing a package substrate
Rudack et al. Through-silicon via plating void metrology using focused ion beam mill
Schmidt et al. Emerging techniques for 2-d/2.5-d/3-d package failure analysis: EOTPR, 3-d x-ray, and plasma fib
Jacobs et al. Light-induced capacitance alteration for nondestructive fault isolation in TSV structures for 3D integration
Altmann et al. Emerging techniques for 3-D integrated system-in-package failure diagnostics
Schmidt et al. Use of 3D X-Ray Microscopy for BEOL and Advanced Packaging Failure Analysis
Lin et al. Application of three-dimensional X-ray microscopy in failure analysis for plastic encapsulated microelectronics