Wilberg et al., 1994 - Google Patents
Design flow for hardware/software cosynthesis of a video compression systemWilberg et al., 1994
View PDF- Document ID
- 1511435964711780506
- Author
- Wilberg J
- Camposano R
- Rosenstiel W
- Publication year
- Publication venue
- Third International Workshop on Hardware/Software Codesign
External Links
Snippet
The implementation of a cosynthesis design flow in the CASTLE (Codesign And Synthesis Tool Environment) system is presented. The design flow generates a synthesizable hardware description and a C, C++, or Fortran compiler for an application-oriented …
- 238000007906 compression 0 title abstract description 25
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
- G06F9/3893—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator
- G06F9/3895—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros
- G06F9/3897—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros with adaptable data path
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/40—Transformations of program code
- G06F8/41—Compilation
- G06F8/44—Encoding
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5045—Circuit design
- G06F17/5054—Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/40—Transformations of program code
- G06F8/41—Compilation
- G06F8/42—Syntactic analysis
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored programme computers
- G06F15/78—Architectures of general purpose stored programme computers comprising a single central processing unit
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/44—Arrangements for executing specific programmes
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/46—Multiprogramming arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/30—Creation or generation of source code
- G06F8/34—Graphical or visual programming
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/30—Creation or generation of source code
- G06F8/36—Software reuse
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/20—Software design
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/68—Processors
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Wang et al. | Hardware/software instruction set configurability for system-on-chip processors | |
| Goodwin et al. | Automatic generation of application specific processors | |
| Camposano et al. | Embedded system design | |
| Nikolov et al. | Systematic and automated multiprocessor system design, programming, and implementation | |
| Hoffmann et al. | A methodology for the design of application specific instruction set processors (ASIP) using the machine description language LISA | |
| Sun et al. | Synthesis of custom processors based on extensible platforms | |
| Sun et al. | Custom-instruction synthesis for extensible-processor platforms | |
| US7475000B2 (en) | Apparatus and method for managing integrated circuit designs | |
| Gokhale et al. | FPGA computing in a data parallel C | |
| Corporaal et al. | Using transport triggered architectures for embedded processor design | |
| Wilberg et al. | Design flow for hardware/software cosynthesis of a video compression system | |
| Chattopadhyay et al. | LISA: A uniform ADL for embedded processor modeling, implementation, and software toolsuite generation | |
| Fauth | Beyond tool-specific machine descriptions | |
| Balboni et al. | Co-synthesis and co-simulation of control-dominated embedded systems | |
| Han et al. | Simulink®-based heterogeneous multiprocessor SoC design flow for mixed hardware/software refinement and simulation | |
| Buyukkurt et al. | Impact of high-level transformations within the ROCCC framework | |
| Buck | A dynamic dataflow model suitable for efficient mixed hardware and software implementations of dsp applications | |
| Liang et al. | The support of MLIR HLS adaptor for LLVM IR | |
| Brand et al. | Orthogonal instruction processing: An alternative to lightweight VLIW processors | |
| Levine et al. | Efficient application representation for HASTE: hybrid architectures with a single, transformable executable | |
| Kavvadias et al. | Hardware design space exploration using HercuLeS HLS | |
| Chattopadhyay et al. | Language-driven exploration and implementation of partially re-configurable ASIPs | |
| Araujo et al. | Platform designer: An approach for modeling multiprocessor platforms based on SystemC | |
| Falk et al. | Integrated modeling using finite state machines and dataflow graphs | |
| Wilberg et al. | Cosynthesis in CASTLE |