[go: up one dir, main page]

Dominic Jawahar et al., 2016 - Google Patents

Self‐gated resonant‐clocked flip‐flop optimised for power efficiency and signal integrity

Dominic Jawahar et al., 2016

View PDF @Full View
Document ID
14893550914643519275
Author
Dominic Jawahar J
Mysore Shivananda Murthy S
Vettuvanam Somasundaram K
Publication year
Publication venue
IET Circuits, Devices & Systems

External Links

Snippet

The clock distribution network primarily comprises of the clock tree and the flip‐flops. The resonant clocking, which drives a clock tree possesses a large potential for a sweeping power minimisation in the clock network. In addition, the clocked flip‐flops, being the crucial …
Continue reading at ietresearch.onlinelibrary.wiley.com (PDF) (other versions)

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G06F1/04Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10Distribution of clock signals, e.g. skew
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01Details
    • H03K3/012Modifications of generator to improve response time or to decrease power consumption
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037Bistable circuits
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/78Power analysis and optimization

Similar Documents

Publication Publication Date Title
Tung et al. Low‐power high‐speed full adder for portable electronic applications
Dokania et al. Circuit‐level design technique to mitigate impact of process, voltage and temperature variations in complementary metal‐oxide semiconductor full adder cells
Jiang et al. Low‐cost single event double‐upset tolerant latch design
Saha et al. Low‐power 6‐GHz wave‐pipelined 8b× 8b multiplier
Lin et al. Single‐ended structure sense‐amplifier‐based flip‐flop for low‐power systems
Upadhyay et al. DFAL: Diode‐Free Adiabatic Logic Circuits
Kumar Mishra et al. Design and analysis of ultra‐low power 18T adaptive data track flip‐flop for high‐speed application
Angeline et al. Design impacts of delay invariant high‐speed clock delayed dual keeper domino circuit
Sabu et al. Design and analysis of power efficient TG based dual edge triggered flip-flops with stacking technique
Geng et al. Design of flip‐flops with clock‐gating and pull‐up control scheme for power‐constrained and speed‐insensitive applications
Singh et al. A Modified Implementation of Tristate Inverter Based Static Master‐Slave Flip‐Flop with Improved Power‐Delay‐Area Product
Dominic Jawahar et al. Self‐gated resonant‐clocked flip‐flop optimised for power efficiency and signal integrity
Garg et al. Low leakage domino logic circuit for wide fan‐in gates using CNTFET
Cooke et al. Energy recovery clocking scheme and flip-flops for ultra low-energy applications
Upadhyay et al. Low‐Power Adiabatic Computing with Improved Quasistatic Energy Recovery Logic
Xiang et al. Design of a low-power pulse-triggered flip-flop with conditional clock technique
Zhang et al. High‐performance and single event double‐upset‐immune latch design
Razmdideh et al. Two novel low power and very high speed pulse triggered flip‐flops
Peiravi et al. Noise‐immune dual‐rail dynamic circuit for wide fan‐in gates in asynchronous designs
Singar et al. A Glitch‐Free Novel DET‐FF in 22 nm CMOS for Low‐Power Application
Razmdideh et al. A novel low power and high speed double edge explicit pulse triggered level converter flip‐flop
Vaithiyanathan et al. Performance analysis of dynamic CMOS circuit based on node‐discharger and twist‐connected transistors
Werner et al. Resilience and yield of flip‐flops in future CMOS technologies under process variations and aging
Lang et al. Design of ternary clock generator
Ramaswami Palaniappan et al. Wide‐input dynamic range 1 MHz clock ultra‐low supply flip‐flop