Mastrandrea et al., 2014 - Google Patents
Statistical characterization, analysis and modeling of speed performance in digital standard cell designs subject to process variationsMastrandrea et al., 2014
View PDF- Document ID
- 12039644047287537803
- Author
- Mastrandrea A
- et al.
- Publication year
External Links
Snippet
Statistical characterization, analysis and modeling of speed performance in digital standard
cell designs subject to process var Page 1 PhD Thesis Statistical characterization, analysis and
modeling of speed performance in digital standard cell designs subject to process variations …
- 238000000034 method 0 title description 8
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
- G06F17/5022—Logic simulation, e.g. for logic circuit operation
- G06F17/5031—Timing analysis
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
- G06F17/5036—Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
- G06F17/5081—Layout analysis, e.g. layout verification, design rule check
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5045—Circuit design
- G06F17/505—Logic synthesis, e.g. technology mapping, optimisation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
- G06F17/504—Formal methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
- G06F17/5072—Floorplanning, e.g. partitioning, placement
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequence
- G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequence by preliminary fault modelling, e.g. analysis, simulation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/70—Fault tolerant, i.e. transient fault suppression
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/84—Timing analysis and optimization
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/78—Power analysis and optimization
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/12—Design for manufacturability
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/10—Probabilistic or stochastic CAD
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/30—Marginal testing, e.g. varying supply voltage
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7673260B2 (en) | Modeling device variations in integrated circuit design | |
| US7721236B2 (en) | Method and apparatus of estimating circuit delay | |
| US8924906B2 (en) | Determining a design attribute by estimation and by calibration of estimated value | |
| US7793239B2 (en) | Method and system of modeling leakage | |
| US20020193959A1 (en) | System and method of determining the noise sensitivity characterization for an unknown circuit | |
| US20090187868A1 (en) | Design of integrated circuits less susceptible to degradations in transistors caused due to operational stress | |
| Olivieri et al. | Logic drivers: A propagation delay modeling paradigm for statistical simulation of standard cell designs | |
| US8813006B1 (en) | Accelerated characterization of circuits for within-die process variations | |
| US8589846B2 (en) | Modeling transition effects for circuit optimization | |
| Lasbouygues et al. | Logical effort model extension to propagation delay representation | |
| Mohanram | Simulation of transients caused by single-event upsets in combinational logic | |
| Andjelkovic et al. | Characterization and modeling of Single Event Transient propagation through standard combinational cells | |
| Sanyal et al. | An efficient technique for leakage current estimation in nanoscaled CMOS circuits incorporating self-loading effects | |
| Liu | Multivariate Adaptive Regression Splines in Standard Cell Characterization for Nanometer Technology in | |
| Subramaniam et al. | A finite-point method for efficient gate characterization under multiple input switching | |
| Mastrandrea | Statistical characterization, analysis and modeling of speed performance in digital standard cell designs subject to process variations | |
| Tang et al. | Statistical transistor-level timing analysis using a direct random differential equation solver | |
| Nandakumar et al. | Statistical static timing analysis flow for transistor level macros in a microprocessor | |
| US6321365B1 (en) | System and method for detecting storage nodes that are susceptible to charge sharing | |
| Sundareswaran | Statistical characterization for timing sign-off: from silicon to design and back to silicon | |
| Bard et al. | Transistor-level tools for high-end processor custom circuit design at IBM | |
| Stamness | Improvement of a propagation delay model for CMOS digital logic circuits | |
| Charafeddine et al. | New voltage and temperature scalable gate delay model applied to a 14nm technology | |
| Λιλίτσης | Power analysis engine implementation for VLSI digital systems | |
| Merrett | Modelling statistical variability within circuits using nano-CMOS technologies |