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Kranitis et al., 2002 - Google Patents

Effective software self-test methodology for processor cores

Kranitis et al., 2002

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Document ID
11719453491608811846
Author
Kranitis N
Paschalis A
Gizopoulos D
Zorian Y
Publication year
Publication venue
Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition

External Links

Snippet

Software self-testing for embedded processor cores based on their instruction set, is a topic of increasing interest since it provides an excellent test resource partitioning technique for sharing the testing task of complex systems-on-chip (SoC) between slow, inexpensive …
Continue reading at www.researchgate.net (PDF) (other versions)

Classifications

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    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
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    • G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
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    • G01R31/318558—Addressing or selecting of subparts of the device under test
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