[go: up one dir, main page]

Gharib et al., 2025 - Google Patents

Efficient Scalable Thermoelectric Modeling of High-Frequency Cylindrical Interconnects for Heterogeneous Package Arrays

Gharib et al., 2025

Document ID
8368179406042911756
Author
Gharib M
Partin-Vaisband I
Publication year
Publication venue
2025 IEEE 75th Electronic Components and Technology Conference (ECTC)

External Links

Snippet

Modern heterogeneous systems rely on dense interconnect arrays—such as through-silicon vias (TSVs), microvias, and copper pillars—where thermoelectric characteristics significantly affect the performance of high-performance computing (HPC) systems. Traditional finite …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G06F17/5036—Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5081—Layout analysis, e.g. layout verification, design rule check
    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/78—Power analysis and optimization
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/04—CAD in a network environment
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/16—Numerical modeling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/82—Noise analysis and optimization
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/80—Thermal analysis and optimization
    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves

Similar Documents

Publication Publication Date Title
Bansal et al. An analytical fringe capacitance model for interconnects using conformal mapping
US8250506B2 (en) Bondwire design
JP3926148B2 (en) Electronic circuit design simulator
Song et al. Full-chip signal integrity analysis and optimization of 3-D ICs
Lim et al. Modeling and analysis of TSV noise coupling effects on RF LC-VCO and shielding structures in 3D IC
Ma et al. An Electrical–Thermal Co-Simulation Model of Chiplet Heterogeneous Integration Systems
Yook et al. Application of system-level EM modeling to high-speed digital IC packages and PCBs
Zhi et al. Time-domain power distribution network (PDN) analysis for 3-D integrated circuits based on WLP-FDTD
Zhao et al. System level power integrity analysis with physics-based modeling methodology
He et al. From layout directly to simulation: A first-principle-guided circuit simulator of linear complexity and its efficient parallelization
Fan et al. Lumped-circuit model extraction for vias in multilayer substrates
Xu et al. Parasitics extraction, wideband modeling and sensitivity analysis of through-strata-via (TSV) in 3D integration/packaging
Gharib et al. An analytical model for high-frequency through silicon vias
Xie et al. Electrical–thermal modeling of through‐silicon via (TSV) arrays in interposer
Kopcsay et al. A comprehensive 2-D inductance modeling approach for VLSI interconnects: Frequency-dependent extraction and compact circuit model synthesis
Gharib et al. Efficient Scalable Thermoelectric Modeling of High-Frequency Cylindrical Interconnects for Heterogeneous Package Arrays
Zhu et al. MTL-based modeling and analysis of the effects of TSV noise coupling on the power delivery network in 3D ICs
CN118862784A (en) A method, device and medium for evaluating total dose effect of through silicon via link based on equivalent circuit model
Zhu et al. A unified finite-element solution from zero frequency to microwave frequencies for full-wave modeling of large-scale three-dimensional on-chip interconnect structures
Yu et al. Loop-based inductance extraction and modeling for multiconductor on-chip interconnects
Min et al. Lumped 3-D equivalent thermal circuit model for transient thermal analysis of TSV array
Lorival et al. An efficient and simple compact modeling approach for 3-D interconnects with IC׳ s stack global electrical context consideration
Jiang et al. EPEEC: Comprehensive SPICE-compatible reluctance extraction for high-speed interconnects above lossy multilayer substrates
Lourandakis et al. RF passive device modeling and characterization in 65nm CMOS technology
Lee et al. A linear-time complex-valued eigenvalue solver for full-wave analysis of large-scale on-chip interconnect structures