[go: up one dir, main page]

Kim et al., 2021 - Google Patents

Z-PIM: A sparsity-aware processing-in-memory architecture with fully variable weight bit-precision for energy-efficient deep neural networks

Kim et al., 2021

Document ID
8311222323236518641
Author
Kim J
Lee J
Lee J
Heo J
Kim J
Publication year
Publication venue
IEEE Journal of Solid-State Circuits

External Links

Snippet

We present an energy-efficient processing-in-memory (PIM) architecture named Z-PIM that supports both sparsity handling and fully variable bit-precision in weight data for energy- efficient deep neural networks. Z-PIM adopts the bit-serial arithmetic that performs a …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52Multiplying; Dividing
    • G06F7/523Multiplying only
    • G06F7/53Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for programme control, e.g. control unit
    • G06F9/06Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/30Arrangements for executing machine-instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/30007Arrangements for executing specific machine instructions to perform operations on data operands
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443Sum of products
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06NCOMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computer systems based on biological models
    • G06N3/02Computer systems based on biological models using neural network models
    • G06N3/06Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored programme computers
    • G06F15/78Architectures of general purpose stored programme computers comprising a single central processing unit
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored programme computers
    • G06F15/80Architectures of general purpose stored programme computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007Architectures of general purpose stored programme computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10Complex mathematical operations
    • G06F17/16Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2207/00Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38Indexing scheme relating to groups G06F7/38 - G06F7/575
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06NCOMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N99/00Subject matter not provided for in other groups of this subclass

Similar Documents

Publication Publication Date Title
Kim et al. Z-PIM: A sparsity-aware processing-in-memory architecture with fully variable weight bit-precision for energy-efficient deep neural networks
Bavikadi et al. A review of in-memory computing architectures for machine learning applications
Yue et al. STICKER-IM: A 65 nm computing-in-memory NN processor using block-wise sparsity optimization and inter/intra-macro data reuse
Ryu et al. BitBlade: Energy-efficient variable bit-precision hardware accelerator for quantized neural networks
Song et al. Hypar: Towards hybrid parallelism for deep learning accelerator array
Zabihi et al. In-memory processing on the spintronic CRAM: From hardware design to application mapping
Jain et al. TiM-DNN: Ternary in-memory accelerator for deep neural networks
US10346347B2 (en) Field-programmable crossbar array for reconfigurable computing
Choi et al. An energy-efficient deep convolutional neural network training accelerator for in situ personalization on smart devices
Heo et al. T-PIM: An energy-efficient processing-in-memory accelerator for end-to-end on-device training
Angizi et al. Dima: a depthwise cnn in-memory accelerator
Angizi et al. Parapim: a parallel processing-in-memory accelerator for binary-weight deep neural networks
Luo et al. AILC: Accelerate on-chip incremental learning with compute-in-memory technology
Wu et al. Pim gpt a hybrid process in memory accelerator for autoregressive transformers
Sie et al. MARS: Multimacro architecture SRAM CIM-based accelerator with co-designed compressed neural networks
Chen et al. Bramac: Compute-in-bram architectures for multiply-accumulate on fpgas
Yan et al. A 28-nm floating-point computing-in-memory processor using intensive-CIM sparse-digital architecture
Hanif et al. Resistive crossbar-aware neural network design and optimization
Singh et al. Cidan-xe: Computing in dram with artificial neurons
Verhelst et al. How to keep pushing ML accelerator performance? Know your rooflines!
Liu et al. Era-bs: Boosting the efficiency of reram-based pim accelerator with fine-grained bit-level sparsity
Yue et al. STICKER-T: An energy-efficient neural network processor using block-circulant algorithm and unified frequency-domain acceleration
Xia et al. Reconfigurable spatial-parallel stochastic computing for accelerating sparse convolutional neural networks
Choi et al. A 47.4 µJ/epoch trainable deep convolutional neural network accelerator for in-situ personalization on smart devices
Gauchi Exploration of reconfigurable tiles of computing-in-memory architecture for data-intensive applications