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Yamamoto et al., 2017 - Google Patents

A systematic methodology for design and worst-case error analysis of approximate array multipliers

Yamamoto et al., 2017

Document ID
7201992663163473963
Author
Yamamoto T
Taniguchi I
Tomiyama H
Yamashita S
Hara-Azumi Y
Publication year
Publication venue
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

External Links

Snippet

Approximate computing is considered as a promising approach to design of power-or area- efficient digital circuits. This paper proposes a systematic methodology for design and worst- case accuracy analysis of approximate array multipliers. Our methodology systematically …
Continue reading at search.ieice.org (other versions)

Classifications

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    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
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