Radmanović, 2023 - Google Patents
Evaluation of binary decision diagrams complexity using relative arithmetic widthRadmanović, 2023
- Document ID
- 5818526107286133601
- Author
- Radmanović M
- Publication year
- Publication venue
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
External Links
Snippet
Many logic synthesis methods are based on the optimization of reduced-order binary decision diagrams (BDDs). The complexity of a BDD greatly depends on the chosen order of variables. Most of the methods find optimal variable ordering focused primarily on some …
- 238000011156 evaluation 0 title abstract description 29
Classifications
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- G06F17/50—Computer-aided design
- G06F17/5045—Circuit design
- G06F17/505—Logic synthesis, e.g. technology mapping, optimisation
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- G—PHYSICS
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- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
- G06F17/5081—Layout analysis, e.g. layout verification, design rule check
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- G06F17/5036—Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
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- G06F17/5018—Computer-aided design using simulation using finite difference methods or finite element methods
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- G—PHYSICS
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- G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
- G06F17/5072—Floorplanning, e.g. partitioning, placement
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- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
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