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Radmanović, 2023 - Google Patents

Evaluation of binary decision diagrams complexity using relative arithmetic width

Radmanović, 2023

Document ID
5818526107286133601
Author
Radmanović M
Publication year
Publication venue
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

External Links

Snippet

Many logic synthesis methods are based on the optimization of reduced-order binary decision diagrams (BDDs). The complexity of a BDD greatly depends on the chosen order of variables. Most of the methods find optimal variable ordering focused primarily on some …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

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    • G06F17/505Logic synthesis, e.g. technology mapping, optimisation
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    • G06F17/5018Computer-aided design using simulation using finite difference methods or finite element methods
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    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
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