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Novac et al., 2010 - Google Patents

DEPENDABILITY ASPECTS REGARDING THE DESIGN OF A CACHE MEMORY.

Novac et al., 2010

Document ID
5581841377372539372
Author
Novac O
Novac M
Vladu E
Vari-Kakas S
Mang G
Indrie L
Publication year
Publication venue
Annals of DAAAM & Proceedings

External Links

Snippet

In this paper, we will present some dependability aspects regarding the design of a cache memory. An important issue in a memory hierarchy is the achievement of a high reliability. Caches provide for efficient read/write access to memory, and their reliability is essential to …
Continue reading at search.ebscohost.com (other versions)

Classifications

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    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0895—Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
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    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
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    • G06F12/12—Replacement control
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    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
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    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
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    • G06F12/1425—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block
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    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory

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