[go: up one dir, main page]

Simon et al., 2003 - Google Patents

A 1.6 Gb/s/pair electromagnetically coupled multidrop bus using modulated signaling

Simon et al., 2003

Document ID
5130492549297819356
Author
Simon T
Amirtharajah R
Benham J
Critchlow J
Knight T
Publication year
Publication venue
2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.

External Links

Snippet

AC coupling and pulse modulation are presented for high speed multidrop busses. A prototype eight module memory bus operates at a 400MHz symbol rate with 4 bits of modulated data per symbol, for 1.6 Gb/s/pair. Test chips in 0.25/spl mu/m 3M CMOS …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; Arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating pulses not covered by one of the other main groups in this subclass
    • H03K5/01—Shaping pulses
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines

Similar Documents

Publication Publication Date Title
US9565036B2 (en) Techniques for adjusting clock signals to compensate for noise
US6625682B1 (en) Electromagnetically-coupled bus system
US7075996B2 (en) Symbol-based signaling device for an electromagnetically-coupled bus system
Sidiropoulos et al. A 700-Mb/s/pin CMOS signaling interface using current integrating receivers
Nakase et al. Source-synchronization and timing vernier techniques for 1.2-GB/s SLDRAM interface
Yeung et al. A 2.4 Gb/s/pin simultaneous bidirectional parallel link with per-pin skew compensation
US6779123B2 (en) Calibrating return time for resynchronizing data demodulated from a master slave bus
Kennedy et al. A 3.6-Gb/s point-to-point heterogeneous-voltage-capable DRAM interface for capacity-scalable memory subsystems
Sidiropoulos High-performance inter-chip signalling
Yang Design of high-speed serial links in CMOS
US5050194A (en) High speed asynchronous data interface
Dickson et al. A 1.4 pJ/bit, power-scalable 16× 12 Gb/s source-synchronous I/O with DFE receiver in 32 nm SOI CMOS technology
US6498512B2 (en) Clock reshaping
US6665624B2 (en) Generating and using calibration information
Zerbe et al. A 5 Gb/s link with matched source synchronous and common-mode clocking techniques
KR100803403B1 (en) Low power modulation
Nishi et al. A 0.190-pJ/bit 25.2-Gb/s/wire inverter-based AC-coupled transceiver for short-reach die-to-die interfaces in 5-nm CMOS
Simon et al. A 1.6 Gb/s/pair electromagnetically coupled multidrop bus using modulated signaling
US6618816B1 (en) System for compensating delay of high-speed data by equalizing and determining the total phase-shift of data relative to the phase of clock signal transmitted via separate path
Tanahashi et al. A 2 Gb/s 21 CH low-latency transceiver circuit for inter-processor communication
Seo et al. A 20-Gb/s/Pin Compact Single-Ended DCC-Less DECS Transceiver With CDR-Less RX Front-End for On-Chip Links
Yeung Design of high-performance and low-cost parallel links
Feng et al. Investigation of DDR T-Topology Port Resistance
Roine A system for asynchronous high-speed chip to chip communication
US6918047B1 (en) Apparatus for high data rate synchronous interface using a delay locked loop to synchronize a clock signal and a method thereof