A recreation of Williams Defender 1981 arcade game for DE10-Lite FPGA dev board, written in VHDL.

Pong game on FPGA Max 10 DE10-Lite, written in VHDL.

ECE 385 Final Project -- Ethernet on MAX10 DE10-Lite FPGA and Nios II soft processor

The Design and Implementation of an Autonomous Mars Rover that has full mapping, remote control and power management capabilities.

Simple verilog project with ability to connect to GPS module using UART and parse NMEA coordinates using finite state machine

VGA demo on the Terasic DE10-Lite FPGA board

VHDL implementation of the Defender arcade game for DE-10 Lite FPGA. For ECE 4110 project.

A recreation of the popular game Tic-Tac-Toe for the DE10-Lite FPGA dev board, in VHDL.

This is a template for projects using the Quartus Prime suite with the DE10-Lite FPGA board.

ADC demo on the Terasic DE10-Lite board with MAX10 FPGA

Simulation platform that enables VHDL-style C++ coding. VCD generation for easy debug. VHDL code generation using C preprocessor. Simple risc-V rv32i SoC example, + Risc-V test suite and gcc bare-metal example. Linux (or WSL) / clang or gcc / risc-v toolchain / quartus required

Nios II Embedded System Dhrystone Test

Train ticket vending machine application designed for execution on an FPGA system. The application allows users to purchase tickets for various destinations and includes maintenance functionalities.

ieee_proposed with names changed to floatfixlib to be compatible with Quartus Prime Lite and support fixed, float, etc.

Terasic Servo Motor Kit (SMK) usage examples

Welcome to the BitBlaster_10bit_Processor! Our custom-designed 10-bit processor, crafted meticulously as part of a project for a Digital Logic Design course at South Dakota State University.

VHDL Project 2018-2019: A university project to discover VHDL and the DE10 LITE 10M50DAF484C7G, just a "Moving Light Emitting Diode". The changing LED states between 10 LEDS creating the illusion that one LED is moving.

Using the DE10 Lite board, read an analogue signal (512 samples) and send the data out of a UART

A Reaction Timer for the DE10 Lite FPGA Written in Verilog HDL