accelsim: update config

romnn · Nov 1, 2023 · 2f2dca4 · 2f2dca4
1 parent 53a05cc
commit 2f2dca4
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Showing 5 changed files with 61 additions and 7 deletions.
diff --git a/accelsim/accel-sim-framework-dev/util/tracer_nvbit/tracer_tool/tracer_tool.cu b/accelsim/accel-sim-framework-dev/util/tracer_nvbit/tracer_tool/tracer_tool.cu
@@ -166,6 +166,17 @@ void instrument_function_if_needed(CUcontext ctx, CUfunction func) {
 
       int opcode_id = opcode_to_id_map[instr->getOpcode()];
 
+      int num_operands = instr->getNumOperands();
+      printf("opcode %s has %d operands: ", instr->getOpcode(), num_operands);
+      for(int i = 0; i < num_operands; ++i){
+        const InstrType::operand_t *op = instr->getOperand(i);
+        printf("%s", InstrType::OperandTypeStr[(int)op->type]);
+        if (i+1 < num_operands) {
+          printf(", ");
+        }
+      }
+      printf("\n");
+
       /* check all operands. For now, we ignore constant, TEX, predicates and 
        * unified registers. We only report vector regisers */
       int src_oprd[MAX_SRC];
@@ -197,12 +208,28 @@ void instrument_function_if_needed(CUcontext ctx, CUfunction func) {
             src_oprd[srcNum] = instr->getOperand(i)->u.reg.num;
             srcNum++;
           }
+        } 
+        /* else if (op->type == InstrType::OperandType::CBANK) {
+          // ADDED: Roman
+          printf("opcode %s has cbank\n", instr->getOpcode());
+          if (i == 0){
+            // find dst reg
+            dst_oprd = instr->getOperand(0)->u.reg.num;
+          }
+          else {
+            // find src regs
+            assert(srcNum < MAX_SRC);
+            src_oprd[srcNum] = instr->getOperand(i)->u.reg.num;
+            srcNum++;
+          }
         }
+        */
       }
 
       do{
         /* insert call to the instrumentation function with its
         * arguments */
+        printf("instrumenting instruction %s\n", instr->getOpcode());
         nvbit_insert_call(instr, "instrument_inst", IPOINT_BEFORE);
 
         /* pass predicate value */

diff --git a/accelsim/gtx1080/gpgpusim.config b/accelsim/gtx1080/gpgpusim.config
@@ -26,10 +26,11 @@
 #-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
 # Pascal NVIDIA TITAN X clock domains are adopted from 
 # https://en.wikipedia.org/wiki/GeForce_10_series
-# edit: GTX 1080 has 1607 base clock instead of 1481
-# edit: GTX 1080 has 2500 mem clock instead of 2750
+# edit: GTX 1080 has 1607 base clock and 1733 boost clock
+# edit: GTX 1080 has 1251 mem clock
 # edit: used same icnt clock as all other configs do that as well (was 2962.0)
--gpgpu_clock_domains 1607.0:1607.0:1607.0:2500.0
+# -gpgpu_clock_domains 1607.0:1607.0:1607.0:2500.0
+-gpgpu_clock_domains 1607.0:1607.0:1607.0:1251.0
 
 # shader core pipeline config
 -gpgpu_shader_registers 65536
@@ -80,6 +81,7 @@
 # The default is NOT to disable the L1 cache, unless cache modifieres is used
 # -gmem_skip_L1D 1
 # -gpgpu_gmem_skip_L1D 1
+# -gpgpu_l1_latency 1
 -gpgpu_l1_latency 82
 
 # 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition).
@@ -130,9 +132,10 @@
 -inter_config_file config_fermi_islip.icnt
 
 # memory partition latency config 
-# -rop_latency 120
--gpgpu_l2_rop_latency 120
--dram_latency 100
+# -gpgpu_l2_rop_latency 1 # was 120
+# -dram_latency 1 # was 100
+-gpgpu_l2_rop_latency 220 # was 120
+-dram_latency 180 # was 100
 
 # dram model config
 -gpgpu_dram_scheduler 1

diff --git a/accelsim/src/build.rs b/accelsim/src/build.rs
@@ -27,6 +27,9 @@ pub fn manifest_path() -> eyre::Result<PathBuf> {
     Ok(path)
 }
 
+// #[derive(Debug, thiserror::Error)]
+// struct MissingOutputPath {}
+
 pub fn output_path() -> eyre::Result<PathBuf> {
     let path = PathBuf::from(std::env::var("OUT_DIR")?);
     let path = path

diff --git a/accelsim/trace/Cargo.toml b/accelsim/trace/Cargo.toml
@@ -31,6 +31,7 @@ utils = { path = "../../utils" }
 
 [build-dependencies]
 color-eyre = "0"
+thiserror = "1"
 duct = "0"
 reqwest = { version = "0", features = ["blocking", "rustls-tls"] }
 bzip2 = "0.4"

diff --git a/accelsim/trace/build.rs b/accelsim/trace/build.rs
@@ -15,10 +15,19 @@ fn decompress_tar_bz2(src: impl AsRef<Path>, dest: impl AsRef<Path>) -> eyre::Re
     Ok(())
 }
 
+#[derive(Debug, thiserror::Error)]
+enum DownloadError {
+    #[error(transparent)]
+    Io(#[from] std::io::Error),
+    #[error(transparent)]
+    Reqwest(#[from] reqwest::Error),
+}
+
 fn download_nvbit(
     version: impl AsRef<str>,
     arch: impl AsRef<str>,
     dest: impl AsRef<Path>,
+    // ) -> Result<(), DownloadError> {
 ) -> eyre::Result<()> {
     let nvbit_release_name = format!("nvbit-Linux-{}-{}", arch.as_ref(), version.as_ref());
     let nvbit_release_archive_name = format!("{nvbit_release_name}.tar.bz2");
@@ -61,7 +70,18 @@ fn build_accelsim_tracer_tool(
 
     let nvbit_path = tracer_nvbit_tool_path.join("nvbit_release");
     if force || !nvbit_path.is_dir() {
-        download_nvbit(nvbit_version, target_arch, &tracer_nvbit_tool_path)?;
+        let res = download_nvbit(nvbit_version, target_arch, &tracer_nvbit_tool_path);
+        match res {
+            Err(err) if !nvbit_path.is_dir() => Err(err),
+            Err(_) => {
+                println!(
+                    "cargo:warning=failed to download nvbit, using {}",
+                    nvbit_path.display()
+                );
+                Ok(())
+            }
+            _ => Ok(()),
+        }?;
     }
 
     let artifact = tracer_nvbit_tool_path.join("tracer_tool/tracer_tool.so");