Pinned Loading

1. pequeno_riscv pequeno_riscv Public

   Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.

   SystemVerilog 52 5

2. pqr5asm pqr5asm Public

   PQR5ASM is a RISC-V Assembler compliant with RV32I

   Python 14 2

3. apb apb Public

   APB master and slave developed in RTL.

   SystemVerilog 9 1

4. debouncer debouncer Public

   Debouncer circuit in Verilog to filter glitches/bounces inherent in switches.

   SystemVerilog 6 2

5. FIFOs FIFOs Public

   Register-based and RAM-based FIFOs designed in Verilog/System Verilog.

   SystemVerilog 14 6

6. skid_buffer skid_buffer Public

   Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.

   SystemVerilog 13 6