8000 Hardware Description Languages · GitHub
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Hardware Description Languages

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  1. bazel_rules_hdl bazel_rules_hdl Public

    Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (https://bazel.build)

    Starlark 172 66

  2. constraints constraints Public

    Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards

    Tcl 49 11

  3. packages packages Public

    Repo to help explain the different options users have for packaging.

    19

  4. awesome awesome Public

    A curated list of awesome resources for HDL design and verification

    Shell 180 25

  5. symbolator symbolator Public

    Forked from kevinpt/symbolator

    Generate symbols from HDL components/modules

    Python 23 8

  6. pyHDLParser pyHDLParser Public

    Forked from kevinpt/hdlparse

    Simple Python parser for extracting HDL (VHDL or Verilog) documentation

    Python 25 12

Repositories

Showing 10 of 17 repositories
  • evolution Public

    FLOSS HDL tooling evolution

    hdl/evolution's past year of commit activity
    TeX 0 Apache-2.0 0 0 0 Updated Nov 12, 2026
  • constraints Public

    Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards

    hdl/constraints's past year of commit activity
    Tcl 49 Apache-2.0 11 5 1 Updated Nov 6, 2026
  • awesome Public

    A curated list of awesome resources for HDL design and verification

    hdl/awesome's past year of commit activity
    Shell 180 CC0-1.0 25 15 (4 issues need help) 3 Updated Nov 6, 2026
  • MINGW-packages Public

    Electronic design automation (EDA) package recipes for MinGW-w64 (MSYS2)

    hdl/MINGW-packages's past year of commit activity
    Shell 8 1 3 (1 issue needs help) 0 Updated Nov 5, 2026
  • containers Public

    Building and deploying container images for open source electronic design automation (EDA)

    hdl/containers's past year of commit activity
    Shell 124 Apache-2.0 25 28 (6 issues need help) 4 Updated Nov 4, 2026
  • bazel_rules_hdl Public

    Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (https://bazel.build)

    hdl/bazel_rules_hdl's past year of commit activity
    Starlark 172 Apache-2.0 66 63 (16 issues need help) 18 Updated Oct 9, 2026
  • conda-eda Public

    Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.

    hdl/conda-eda's past year of commit activity
    Shell 101 Apache-2.0 29 76 22 Updated Jan 30, 2025
  • pyHDLParser Public Forked from kevinpt/hdlparse

    Simple Python parser for extracting HDL (VHDL or Verilog) documentation

    hdl/pyHDLParser's past year of commit activity
    Python 25 MIT 55 5 3 Updated Mar 1, 2024
  • symbolator Public Forked from kevinpt/symbolator

    Generate symbols from HDL components/modules

    hdl/symbolator's past year of commit activity
    Python 23 MIT 50 3 2 Updated Feb 6, 2023
  • conda-build-prepare Public
    hdl/conda-build-prepare's past year of commit activity
    Python 0 Apache-2.0 1 1 1 Updated Jan 16, 2023
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