8000 Narrow logical right shifts used only through low bit slices by Novpolina · Pull Request #5246 · google/xls · GitHub
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Narrow logical right shifts used only through low bit slices - #5246

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Novpolina:fix/narrow-truncated-right-shifts
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Narrow logical right shifts used only through low bit slices#5246
Novpolina wants to merge 1 commit into
google:mainfrom
Novpolina:fix/narrow-truncated-right-shifts

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@Novpolina
@Novpolina Novpolina commented Nov 3, 2026
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Narrow logical right shifts used only through low bit slices

Summary

Replace a wide logical right shift whose result is observed only through low bit slices with a narrow dynamic_bit_slice.

Motivation

In the single-proc CRC module, one byte is extracted from a 128-bit payload, but optimized IR and generated SystemVerilog retain a full 128-bit dynamic right shift:

shifted = shrl(payload, shift)
data = bit_slice(shifted, start=0, width=8)

This change exposes the operation as dynamic_bit_slice(payload, shift, width=8) instead of a full-width barrel shifter. Since the shift is a multiple of eight, the existing optimization pipeline can collapse it into a 16-to-1 mux of bytes.

Testing

bazel test \
  //xls/passes:bit_slice_simplification_pass_test \
  //xls/passes:optimization_pass_pipeline_test

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