8000 fommil (Sam Halliday) / Starred · GitHub
[go: up one dir, main page]

Skip to content
View fommil's full-sized avatar
🤖
making microchips
🤖
making microchips

Block or report fommil

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Content in all repositories owned by your account will be closed.
Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Showing results

A plate solving telescope finder based around a Raspberry PI and RPI HQ Camera

Jupyter Notebook 258 63 Updated Nov 11, 2026

Resilience Structures for Cats Effect

Scala 3 1 Updated Oct 14, 2026

A free, open source C# framework for making games, or your own game engine. Direct access to native APIs and Vulkan, with the low-level libraries around them. The foundation under Kitten Space Agen…

C# 2,460 162 Updated Nov 12, 2026

Tiny Tapeout shuttle SKY 26d

Verilog 6 1 Updated Nov 11, 2026
Python 4,652 627 Updated Sep 23, 2026

Spade HDL for BreakingTTAPs

Python 49 5 Updated Sep 19, 2026

Linus learns analog circuits

C 2,493 132 Updated Nov 6, 2026

open hardware for LLM acceleration

Python 5 Updated Oct 1, 2026

A physical digital pet you keep alive — ESP32-S3 firmware and an Android app that does all the thinking on-device.

Kotlin 56 3 Updated Sep 8, 2026

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

C++ 1,975 318 Updated Oct 29, 2026

A simple utility for running exhaustiveness checks on Go "sum types."

Go 454 24 Updated Mar 21, 2025

A simple utility for running exhaustiveness checks on Go "sum types."

Go 59 10 Updated Oct 24, 2026

Exhaustiveness checks for your interface "sum types" using a lightweight naming convention + `go vet`.

Go 18 Updated Nov 6, 2025

Submission template for Tiny Tapeout IHP shuttles - Verilog HDL Projects

Verilog 92 225 Updated Oct 28, 2026

Experiments with composable lock-free concurrency

Scala 25 1 Updated Nov 5, 2026

Chisel: A Modern Hardware Design Language

Scala 4,833 667 Updated Nov 11, 2026

Open-Source Framework for Numerically-Tailored Computations This project is "An Open-Source Framework for Efficient Numerically-Tailored Computations", hence the acronym OSFNTC. The title of the co…

Fortran 26 2 Updated Jun 15, 2023
Verilog 3 1 Updated Jul 11, 2022
Verilog 11 1 Updated Mar 21, 2022

Exploring if we can write lazy HDL and let the OSS tools optimize our sloppiness. Spoiler: We absolutely can!

Verilog 2 Updated May 1, 2026

Pushing the bf16 multiplication clock frequency to the max on the nominal corner on IHP 130nm 5L node.

Python 17 Updated Mar 29, 2026

RTL implementation of a performance/area optimized bfloat16 adder and multiplication.

Verilog 40 3 Updated Mar 28, 2026

A minimal GPU design in Verilog to learn how GPUs work from the ground up

SystemVerilog 13,228 1,276 Updated Aug 18, 2024
Verilog 72 7 Updated Jul 13, 2026
Assembly 16 3 Updated Aug 6, 2025
Assembly 39 10 Updated Nov 6, 2026

Chord-Conditioned Melody Transformer

Python 39 9 Updated Jun 27, 2021

Generate monophonic melodies with machine learning using a basic LSTM RNN

Python 168 33 Updated Aug 20, 2018
Verilog 1 Updated Nov 27, 2024

ASIC implementation flow infrastructure, successor to OpenLane

Python 633 112 Updated Nov 11, 2026
Next
0