8000 dobios (Amelia Dobis) / Starred · GitHub
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@llvm @YosysHQ @chipsalliance @H-PixelDroid @chiselverify @GameLab-UNIL-EPFL

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Showing results
OCaml 8 1 Updated Oct 30, 2026
OCaml 40 12 Updated Oct 30, 2026

New implementation of protocols

Rust 15 Updated Nov 6, 2026

Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)

SystemVerilog 2,162 831 Updated Nov 6, 2026

Btor2 parser, circuit mitter, and code optimizer

Python 1 Updated Oct 9, 2026

CIRCT and Yosys interoperability, demonstrated with CHISEL

C++ 18 1 Updated Feb 3, 2026

Animated sprite editor & pixel art tool (Windows, macOS, Linux)

C++ 40,729 9,411 Updated Nov 4, 2026
Scala 28 25 Updated Dec 4, 2025

Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pipelines.

C++ 1,431 101 Updated Nov 5, 2026

Agile Hardware Design Course

Scala 35 12 Updated Nov 3, 2026
Python 12 1 Updated Nov 6, 2026
Verilog 4 Updated Sep 7, 2026

Hardware Formal Verification Tool

Rust 125 31 Updated Nov 4, 2026
Python 32 5 Updated Nov 2, 2025

design and verification of asynchronous circuits

Python 52 1 Updated Nov 3, 2026

The Task Parallel System Composer (TaPaSCo)

Verilog 128 30 Updated Jun 23, 2026
TeX 4 1 Updated May 29, 2026

Bluespec Compiler (BSC)

Haskell 1,150 187 Updated Nov 6, 2026

Formal specification and verification of hardware, especially for security and privacy.

Coq 133 21 Updated May 19, 2022

Circuit IR Compilers and Tools with memory support

C++ 1 Updated Sep 10, 2026

Rust bindings for CIRCT

Rust 19 1 Updated Apr 20, 2024

Perfect Green Screen Keys

Python 15,015 910 Updated May 28, 2026
Scala 2 Updated Sep 29, 2026

Pony is an open-source, actor-model, capabilities-secure, high performance programming language

Pony 6,216 440 Updated Nov 6, 2026

An experiment in hardware accelerated DSLs and parallel algorithms for signal processing applications.

Rust 10 Updated Oct 22, 2025

High level synthesis language for hardware design

C++ 108 15 Updated Nov 4, 2026

Yosys Open SYnthesis Suite

C++ 4,873 1,200 Updated Nov 6, 2026

Haskell to VHDL/Verilog/SystemVerilog compiler

Haskell 1,626 172 Updated Nov 6, 2026

A Hardware Description Language based on the Rust Programming Language

Verilog 330 24 Updated Apr 21, 2026
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