[go: up one dir, main page]
Skip to content

Issues: byuccl/spydrnet

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

43 Open 82 Closed
43 Open 82 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Assignee
Filter by who’s assigned
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Issues list

Flatten cannot handle multiple instances of one definition in another definition. documentation Improvements or additions to documentation
#220 opened Feb 14, 2024 by zhuguiyuan
2
EDIF files generated by Atmel CPLD fitter unparsable. resolved? Believed to be resolved and ready to close
#215 opened Oct 15, 2023 by peterzieba
11
Getting recursion error when parsing a netlist resolved? Believed to be resolved and ready to close
#213 opened Oct 5, 2023 by arun-chaubey
7
Create CoLab examples documentation Improvements or additions to documentation
#207 opened May 15, 2023 by wirthlin
Include type hinting
#203 opened Apr 3, 2023 by agg23
1
Handling Intel architecture definitions
#202 opened Apr 3, 2023 by agg23
1
[verilog] Primitives
#201 opened Apr 2, 2023 by agg23
4
Distinguishing pins in multi-bit ports resolved? Believed to be resolved and ready to close
#196 opened Mar 18, 2023 by jgoeders
5
Delete Old Branches
#192 opened Oct 19, 2022 by jacobdbrown4
5
Transformation to and from EBLIF
#191 opened Aug 12, 2022 by emonlux
1
Make SpyDrNet internals completely generic
#185 opened Aug 2, 2022 by jacobdbrown4
2
Case Sensitivity - EDIF composer
#182 opened Jul 1, 2022 by emonlux
10
Setting correct top module when parsing netlist from Lattice resolved? Believed to be resolved and ready to close
#178 opened May 20, 2022 by jacobdbrown4
4
Can you store an instance's information in an HRef object? resolved? Believed to be resolved and ready to close
#155 opened Oct 14, 2021 by jacobdbrown4
9
EDIF parser pytest coverage
#151 opened Aug 2, 2021 by jacobdbrown4
Create a built in construct and move module/cell parameters out of the metadata
#145 opened Jun 17, 2021 by thunder-hammer
1
Create Xilinx library minor Minor release issue
#144 opened Jun 7, 2021 by wirthlin
@benglines
5
Create a back end to support the SymbiFlow interchange format
#143 opened Jun 7, 2021 by wirthlin
Clean up the namespace managers' implementations
#142 opened Jun 2, 2021 by thunder-hammer
@thunder-hammer
2
Verilog Parser features required to parse Quartus Prime .vo/vqm files
#141 opened May 25, 2021 by thunder-hammer
@thunder-hammer
4
Analyze and improve constant support Verilog Parser
#140 opened May 25, 2021 by thunder-hammer
instance.get_pins() vs instance.pins major Major release issue
#139 opened May 24, 2021 by jacobdbrown4
6
Documentation about building the documentation
#138 opened May 24, 2021 by thunder-hammer
Need to document the examples good first issue Good for newcomers
#136 opened May 17, 2021 by wirthlin
1
Additional visualization example file
#130 opened Apr 30, 2021 by thunder-hammer
@jacobdbrown4
6
ProTip! no:milestone will show everything without a milestone.