I am a systems-focused software engineer specializing in low-level C/C++ programming, computer architecture, and hardware acceleration. My passion lies in squeezing every bit of performance out of hardware—whether it's optimizing sparse linear algebra kernels for RISC-V Vector (RVV) processors or hardening transaction logic in Web3 interoperability frameworks.
- rv-sparse (LFX Mentorship): Accelerating sparse matrix multiplication (SpGEMM) using RISC-V Vector Extension (RVV 1.0) intrinsics.
- Hyperledger Cacti: Hardening the SATP (Secure Asset Transfer Protocol) logic and optimizing transaction validation services.
- High-Performance AI: Integrating edge-AI backends (Llama.cpp, ONNX) for constrained hardware environments.
| Category | Technologies |
|---|---|
| Languages | C, C++, TypeScript, Python, JavaScript, Go |
| Systems & Arch | RISC-V (RVV), QEMU, x86-64, Computer Architecture, Memory Management |
| Web3 & Infrastructure | Hyperledger Cacti, Fabric, Besu, Docker, Kubernetes, Linux Foundation Projects |
| Tools & OS | Linux (Ubuntu/WSL), Git, CMake, Makefile, Valgrind, GDB |
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Two-Phase Gustavson SpGEMM: Implemented a memory-safe, two-phase algorithm in pure C, eliminating
$O(K)$ dense scans and reducing heap allocations in the inner loops. - RVV 1.0 Acceleration: Prototyping gather/scatter-based kernels to exploit hardware-level parallelism on RISC-V.
- SATP Validation Logic: Refactored monolithic transaction handlers into decoupled, maintainable services.
- Codebase Hardening: Addressed structural TODOs in crash managers and improved CI/CD reliability for the monorepo.
- EVerest (LF Energy): Contributed to the modular framework for EV charging infrastructure.
- KubeSlice: Worked on partial mesh support for multi-cluster networking.
- LinkedIn: Abhayraj Jaiswal
- Email: abhayraj916146@gmail.com
- GitHub: abhayrajjais01
"Complexity is the enemy of performance. I aim to build systems that are as efficient as they are robust."