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On arm64, double-buffer the x/v/x2 rails by row parity so the t-1 shifted rails become plain unaligned loads from the previous row's padded buffer, removing three vext rail-shifts and three carry moves per inner iteration. The row boundary byte is inserted with a single lane-0 write (ksw_insert0). Gated by KSW_EXTD2_NEON_KERNEL (set only under __ARM_NEON): x86/SSE keeps the original single-buffer path, where the alignr shift is already one cheap op and double-buffering regresses short reads. A macro layer lets both kernels share the loop bodies, and the rails store identical values on both paths, so the arm64 output is byte-identical to stock across the full int8 parameter domain -- verified by a 104k-call differential sweep that deliberately spans q+e and q2+e2 past the int8 overflow edge, plus bench --check (120k pairs) and full-aligner SAM identity on real reads across four flag modes on both arches. +4-11% on the extd2 dual-gap kernel on Graviton4 at qlen 100/150/250, and neutral/byte-identical on x86 -- the #1 aligner hotspot.
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What
Optimizes minibwa's #1 aligner hotspot — the
extd2dual-gap (two-piece affine, Suzuki-Kasahara) Smith-Waterman extension kernel — on arm64/NEON only, on top of the existingperf/ksw2-extension-kernelsfeature.The x/v/x2 DP rails are double-buffered by row parity, so the
t-1shifted rails become plain unaligned loads from the previous row's padded buffer instead of avextshift + carry-move per rail per inner iteration (three of each removed). The row boundary byte is inserted with a single lane-0 write. A macro layer (__dp_store_*,__dp_u8/__dp_v8,__dp_code_block3) lets the two kernels share the loop bodies.Gated by
KSW_EXTD2_NEON_KERNEL, which is set only under__ARM_NEON. On x86/SSE the original single-buffer kernel is used verbatim, because there the shift is already a single cheap_mm_alignr_epi8and double-buffering mildly regresses short reads — the same arm64-only guarding rationale used elsewhere in the ksw2 kernels. The rails store identical values on both paths, so output is byte-identical to the current kernel on both ISAs.Performance (
bwa-bsw-bench, arm64 Graviton4 c8g, best-of-7 ×2)x86 (c6a, AVX2 host): neutral (1.00×), byte-identical — the guard leaves the x86 path unchanged.
Correctness
./sw_bench --check --mode extd2: PASS — 120,000 pairs identical in score and CIGAR.KSW_EXTD2_NEON_KERNEL=0vs=1, same source) with 0 divergences, deliberately sweepingq+e/q2+e2past the int8 overflow edge (10k+ draws withqe+qe2 > 128) so the byte-identity holds across the full parameter domain, not just realistic scoring.default/-u/-b MD/ single-end on real WGS reads (~100k records each), on both arm64 and x86.Draft,
feature-labeled review vehicle — installation is the manifest's job, not this PR.