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RISC-V-rv32i Public
This is rv32i verilog design and it works fine for all instrcutions except lbu , lhu , ecall,ebreak
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UART-protocol Public
UART - RTL Design and Verification
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Automatic-washing-machine Public
This project proposes to demonstrate the capabilities and scope of Verilog HDL by implementing the control system of an automatic washing machine. The above mentioned objective by implementing the …
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Router-1-x-3- Public
Router 1 x 3 verilog implementation
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simple-MIPS32-processor Public
A pipelined implementation of MIPS32 processor using Verilog HDL MIPS32 is a Reduced Instruction Set Computer (RISC) architecture, and here, this particular processor is designed in Verilog HDL wit…
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Booths-multiplier Public
booth's multiplier defined by datapath and control path , where controller generates different control signals which are used by different modules to generate product
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DA-Based-LMS-Adaptive-filter Public
Distributed arithmetic (DA) is another way of implementing a dot product where one of the arrays has constant elements. The DA can be effectively used to implement FIR, IIR and FFT type.The DA logi…
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8-3-Priority-encoder Public
A 4 to 2 priority encoder has 4 inputs : Y3, Y2, Y1 & Y0 and 2 outputs : A1 & A0. Here, the input, Y3 has the highest priority, whereas the input, Y0 has the lowest priority. In this case, even if …
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Parallel-Adder-subtractor Public
4 bit parallel adder/ subtractor circuit does both addition and subtraction by using 2 ripple carry adders and some xor gates
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SPI-protocol Public
SPI is a synchronous, full duplex master-slave-based interface. The data from the master or the slave is synchronized on the rising or falling clock edge based on mode .Both master and slave can tr…
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Mod-N-Counter Public
Counters are sequential logic devices that follow a predetermined sequence of counting states triggered by an external clock (CLK) signal. Modulus Counters, or MOD counters, are defined based on th…
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JK-Flipflop Public
The J-K flip-flop is the most versatile of the basic flip-flops. It has the input- following character of the clocked D flip-flop but has two inputs,traditionally labeled J and K. If J and K are di…
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D-flipflop Public
The D flip-flop is an edge triggered device which transfers input data to Q on clock rising or falling edge.
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Parallel-IN-Parallel-OUT Public
In this type of register, there are no interconnections between the individual flip-flops since no serial shifting of the data is required. Data is given as input separately for each flip flop and …
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Parallel-IN-Serial-OUT Public
In this shift register, we can apply the parallel inputs to each D flip-flop by making Preset Enable to 1. For every positive edge triggering of clock signal, the data shifts from one stage to the …
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Serial-IN-Parallel-OUT Public
In this shift register, we can send the bits serially from the input of left most D flip-flop. Hence, this input is also called as serial input. For every positive edge triggering of clock signal, …
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Serial-IN-Serial-OUT Public
In this shift register, we can send the bits serially from the input of left most D flip-flop. Hence, this input is also called as serial input. For every positive edge triggering of clock signal, …
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Universal-Shift-Register Public
Universal Shift Register is a register which can be configured to load and/or retrieve the data in any mode (either serial or parallel) by shifting it either towards right or towards left. In other…
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UP-DOWN-Counter Public
4 bit up down counter counts from 0000 to 1111 if control input is set HIGH ,else it would count from 1111 to 0000. it can be build by cascading 4 nos of D flipflops with a mux at the input node to…