A hardware implementation of a 4-bit signed multiplier using stochastic computing — an approximate computing technique that trades a small amount of numerical accuracy for a drastically simpler, more area/power-efficient multiplication circuit compared to a conventional array or Booth multiplier.
Conventional multipliers scale in area and power roughly quadratically with bit-width. Approximate computing techniques exploit the fact that many application domains (image processing, machine learning inference, sensor fusion) can tolerate small numerical errors in exchange for significant hardware savings. This project implements one such technique — stochastic logic multiplication — where numbers are represented as random bitstreams and multiplication reduces to simple bit counting instead of full binary multiplication logic.
Two operands are represented in sign-magnitude form. The magnitude of X is converted into a stochastic bitstream (a serial sequence of bits where the probability of seeing a 1 is proportional to X's magnitude). This bitstream is then gated by a down-counter running for Y cycles, and the number of 1s observed approximates the product X × Y. Sign is tracked and corrected separately via XOR and two's complement.
┌──────────┐
│ LFSR │──rand_val──┐
└──────────┘ │
▼
X[2:0] ──────────► ┌──────────┐
│ SNG Unit │──S (bitstream)──┐
└──────────┘ │
▼
Y[2:0], start ──────────────────────────► ┌──────────────┐
│ Multiplier │──raw_product
│ Core │──done
└──────────────┘
│
X[3] XOR Y[3] (sign_z) ──────────────────────────┤
▼
┌────────────────┐
│ Sign Correction│──Z (final signed result)
└────────────────┘
| Module | Description |
|---|---|
lfsr_4bit.v |
4-bit Fibonacci LFSR with XOR feedback taps, empirically verified to produce a maximal-length 15-state pseudo-random cycle, used as the source driving stochastic bit generation. |
sng_unit.v |
Stochastic Number Generator — compares the LFSR output against X's magnitude each cycle to produce a bitstream S where P(S=1) ∝ X. |
multiplier_core.v |
Down-counts for Y cycles while gating and counting the incoming bitstream S, accumulating the approximate raw product magnitude. |
sign_correction.v |
Applies two's complement correction to the raw magnitude based on the XOR of input sign bits, producing the final signed 4-bit product Z. |
approx_multiplier_top.v |
Top-level module wiring the LFSR, SNG, multiplier core, and sign correction into the complete pipeline. |
tb_lfsr.v— validates the LFSR produces a non-repeating pseudo-random sequence over its 15-state cycle.tb_core.v— unit-level testbench for the multiplier core against a range ofYvalues.tb_top.v— exhaustive verification: simulates all 225 valid signed 4-bit × 4-bit input combinations (excluding the invalid negative-zero encoding) against a software golden model, and reports pass/fail plus overall stochastic accuracy.
Simulated with Icarus Verilog. Exhaustive testing across all 225 valid input pairs shows ~77% exact match against the ideal (golden-model) product — consistent with the expected accuracy/hardware-cost tradeoff of stochastic computing at this short bitstream length. Accuracy can be improved by extending the bitstream window (i.e., using a longer LFSR and counting for more cycles) at the cost of latency.
# Full pipeline, exhaustive verification (225 cases)
iverilog -o tb_top.out approx_multiplier_top.v lfsr_4bit.v multiplier_core.v sign_correction.v sng_unit.v tb_top.v
vvp tb_top.out
# LFSR standalone
iverilog -o tb_lfsr.out lfsr_4bit.v tb_lfsr.v
vvp tb_lfsr.out- Sign-magnitude representation: bit 3 is sign, bits [2:0] are magnitude — chosen to make stochastic bitstream generation straightforward (bitstreams are naturally unsigned probability sequences).
- Non-zero LFSR seed: the LFSR must never be seeded with
0000, as an all-zero state is a fixed point that would produce a constant (non-random) bitstream. - Accuracy vs. cost tradeoff: this is the central idea of the design — a conventional 4×4 signed multiplier would need a full partial-product array; this design replaces that with an LFSR, one comparator, and a counter, at the cost of inexact results.
- Parameterize bit-width beyond 4 bits.
- Extend the bitstream window length to characterize the accuracy/latency/area tradeoff curve.
- Compare synthesized area/power against a conventional Wallace-tree multiplier.