GitHub - IgPant/VHDL: Some interesting Uni projects using hardware description language. A state machine, synchronous 4 and 8 bit up/down counters with Hold, Clear and Reverse.

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Some interesting Uni projects using hardware description language. A state machine, synchronous 4 and 8 bit up/down counters with Hold, Clear and Reverse.

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Name		Name	Last commit message	Last commit date
Questão 1		Questão 1
Questão 2		Questão 2
VHDL.pdf		VHDL.pdf

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Some interesting Uni projects using hardware description language. A state machine, synchronous 4 and 8 bit up/down counters with Hold, Clear and Reverse.

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