Code Generation

RISCV For discussing RISCV code generation in LLVM. Mips Ask questions about the Mips backend. WebAssembly For questions about the WebAssembly backend. AMDGPU This category is for discussions specific to both the development of the AMDGPU target in upstream LLVM and its use inside the LLVM project and by outside compiler frontends (e.g. LLPC, Mesa). PowerPC Discuss the PowerPC backend. X86 For questions about the X86 backend. ARM For questions about the Arm backend. Common CodeGen Infrastructure This category is for common code generation infrastructure related to all backends. AArch64 For questions about the AArch64 backend.

Topic	Replies	Views	Activity
About the Code Generation category Code Generation	4	963	January 11, 2022
MachineScheduler: why does the heuristic unconditionally relax the pressure limit by LiveThru? Common CodeGen Infrastructure regalloc , llvm	2	84	October 16, 2026
[RFC] Add widening multiply libcalls to RuntimeLibcalls Common CodeGen Infrastructure rfc , avr , msp430 , riscv , runtime	4	106	October 16, 2026
[RFC][Arm] Fixing function size estimation (2) ARM	2	157	October 13, 2026
[RFC] Clarifying NVPTX compute capability and PTX version handling Code Generation nvptx	11	471	October 11, 2026
[RFC] Respecting freeze semantics in backends Common CodeGen Infrastructure llvm	22	516	October 11, 2026
[RFC] Renesas SuperH Backend Code Generation rfc , llvm	37	1242	October 9, 2026
CANCELLED RISC-V LLVM sync-up call October 8th 2026 RISCV	0	51	October 7, 2026
Memory Corruption in LLVM Common CodeGen Infrastructure	3	242	October 2, 2026
Zicfilp func-sig label scheme conventions RISCV riscv	7	154	October 2, 2026
mayLoad = 1 for RISCV PseudoLA instruction RISCV riscv	2	74	October 1, 2026
[RFC] RISC-V: a target for software (interpreted) rather than hardware (executed) RISCV riscv	13	506	September 26, 2026
RISC-V LLVM sync-up call September 24th 2026 RISCV	0	48	September 23, 2026
LLVM ABI library support for AArch64 AArch64	5	287	September 21, 2026
Beginner guide for LLVM backend development for AArch64 Common CodeGen Infrastructure arm64 , llvm	3	273	September 21, 2026
[RFC] Exposing Pre-RA Scheduling for Search and ML Experimentation Common CodeGen Infrastructure	8	284	September 11, 2026
Remove Ventana Conditional Ops and Veyron V1 Defintion RISCV riscv	3	149	September 10, 2026
RISC-V LLVM sync-up call Septemer 10th 2026 RISCV	0	40	September 10, 2026
[RFC] AArch64: Ternary select-accumulate to SDOT lowering AArch64 arm64 , llvm	0	61	September 7, 2026
[RFC] Change MIR to use block arguments instead of phis Code Generation	6	1634	September 3, 2026
CANCELLED RISC-V LLVM sync-up call August 27th 2026 RISCV	0	55	August 26, 2026
AArch64 Vector PCS on Darwin/Mach-O: support status and ABI contract? AArch64 arm64 , macos , clang	0	66	August 26, 2026
Shrink Wrap Save/Restore Points Splitting Common CodeGen Infrastructure	26	1834	August 25, 2026
Per Processor Costing for RISCV RISCV riscv , llvm	12	614	August 24, 2026
[RFC][Clang][ARM] Proactive stack overflow trapping for bare-metal Cortex-M ARM arm , clang , embedded	3	197	August 17, 2026
RISC-V LLVM sync-up call August 13th 2026 RISCV	0	75	August 13, 2026
[wincall] Propose a new x86_64 windows calling convention wincall X86 llvm	0	129	August 11, 2026
Error in backend: Can't handle live physical register dependency! Common CodeGen Infrastructure	3	225	July 30, 2026
CANCELLED RISC-V LLVM sync-up call July 30th 2026 RISCV	0	76	July 29, 2026
How to define multiple RegisterTuples for the same registers? Common CodeGen Infrastructure	2	154	July 22, 2026