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anycore-riscv-src

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forked from bring-your-own-core/anycore-riscv-src

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The RTL source for AnyCore RISC-V

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Name		Name	Last commit message	Last commit date
ISA		ISA
bist		bist
chip_top		chip_top
configs		configs
core_top		core_top
dcache		dcache
decode		decode
dispatch		dispatch
execute		execute
fetch		fetch
icache		icache
include		include
issue		issue
lib		lib
lsu		lsu
power_spec		power_spec
rams		rams
rams_configurable		rams_configurable
rams_partitioned		rams_partitioned
regRead		regRead
rename		rename
retire		retire
serdes		serdes
testbenches		testbenches
writeback		writeback
Copyright		Copyright
LICENSE		LICENSE
README.md		README.md
flist		flist
tags		tags

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anycore

This contains the RTL for Anycore and associated simulation and synthesis framework for the latest RISCV based development of AnyCore

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The RTL source for AnyCore RISC-V

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