Pics from Jordon Kashanchi's talk at #DAC2026. Sitting on both the tooling side and the silicon-delivery side gives us a different read on this: there's still a lot of AI leverage left to capture at what we call the coordination layer, the layer where requirements, decisions, and verification stay tied together. Our case: every AI-generated output at Visibl Semiconductors has to trace back to a real engineering decision and be checkable against real tools. Case in point — G1, our high-voltage gate driver chip (mature BCD process, a fabrication process combining bipolar, CMOS, and DMOS transistors on one chip): - Design assumed the bond wires (fine wires linking chip to package) could handle the output current - Packaging review quantified the actual limit and caught the gap - Layout changed before tape-out (design finalized, sent to fab for manufacturing), current split across multiple pads, bond wires paralleled The model: every requirement gets a named owner, a verification method, and a signoff gate before it ships. AI speeds up the checking. Engineers own the risk calls. Traditional ASIC economics price out companies that need custom silicon. Our AI-native execution layer cuts development cost and time on mature nodes, so hardware teams can bring custom silicon to market that actually survives sign-off and production, and ultimately field more competitive products that make them category leaders. #Semiconductors #ChipDesign #EDA #AI #ASIC #SiliconDesign
Visibl Semiconductors (YC W26)
Software Development
San Francisco, California 773 followers
A faster, more cost-effective path to custom silicon
About us
Visibl gives hardware companies a faster, in-budget path to custom silicon — from chip concept to production. A chip designed for your exact product means lower power, better performance, lower BOM cost at volume, and a supply chain you own.
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www.visiblsemi.com
External link for Visibl Semiconductors (YC W26)
- Industry
- Software Development
- Company size
- 2-10 employees
- Headquarters
- San Francisco, California
- Type
- Privately Held
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San Francisco, California, US
Employees at Visibl Semiconductors (YC W26)
Updates
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We're presenting at DAC, The Chips to Systems Conference 2026. Jordon Kashanchi, Co-Founder of Visibl Semiconductors (YC W26), is giving the talk "AI-Native Workflows from Architecture to Production Readiness": how we design custom ASICs from spec to physical silicon, and what we learned from our first tapeout. Monday, July 27 · 4:00-5:00 PM PDT Exhibitor Forum, DAC, The Chips to Systems Conference, Long Beach https://lnkd.in/gePFTSTd #DAC2026 #semiconductors #ASIC
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We are incredibly excited to launch Visibl: The Coordination Layer for Chip Design. Check out our launch below!
Visibl Semiconductors (YC W26) is building the first coordination layer for chip design. As chip teams scale, critical workstreams drift out of sync and issues surface late, driving costly delays ($XM+) and months of rework before tapeout. Visibl’s long-term vision is to build end-to-end AI systems that shrink chip design from years to weeks. The team is starting with coordination because that’s where design intent breaks first. Visibl was founded by Bryce Neil and Jordon Kashanchi, who have built production systems and custom AI chips at Microsoft, Intel Corporation, Arm, Deloitte OmniaAI, and SST. They started Visibl after repeatedly seeing coordination bottlenecks delay integration and tapeout. Seeing Visibl in action will change how your team approaches chip design. Book a demo at www.visiblsemi.com Congrats on the launch Bryce Neil and Jordon Kashanchi! https://lnkd.in/ghHgeqKZ
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Lots of people have heard of Visibl Semiconductors (YC W26) but don't know what we actually do. We will be at some big conferences in the coming weeks, sharing Visibl with top semiconductor teams. Send us a DM if you plan to be there, we would love to meet you! ISSCC 2026 - International Solid-State Circuits Conference (San Francisco), Feb 16–18 https://www.isscc.org/ DVCon 2026 - Design & Verification Conference (Santa Clara), March 2–5 https://dvcon.org/ NVIDIA GTC - GPU Technology Conference (San Jose), March 16 https://lnkd.in/g_baWc9
The YC batch has been awesome so far. The intimate advice from AI lab and deep-tech leaders is helping us scale our vision and take Visibl Semiconductors to the next level. We’re taking that momentum on the road! Let's talk AI in chip design at these conferences around the valley: 📍 ISSCC 2026 (San Francisco) | Feb 16-18 📍 DVCon 2026 (Santa Clara) | March 2-5 📍 NVIDIA GTC (San Jose) | March 16 If you’re working on the cutting edge of AI hardware and silicon methodology, I'd love to hear what you’re building. Drop a comment or DM me if you’ll be around! #Semiconductors #ISSCC2026 #DVCON2026 #NVIDIAGTC #YCombinator
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Big Announcement 🎉 We are thrilled to share that Visibl Semiconductors is part of the Y Combinator Winter 2026 batch! 🟧 Check us out: https://lnkd.in/gmSpcwCG
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Big Announcement 🎉 Jordon Kashanchi has joined Visibl Semiconductors as Co-Founder and CTO! Jordon joins us from Microsoft, where he spent the last 2.5 years working on custom silicon for Azure Maia. Bryce Neil and Jordon met last year in San Francisco and bonded over a shared obsession: solving the execution bottlenecks in modern chip design. Their partnership is set to transform the industry. Check us out: https://lnkd.in/gaQgGj6g