| Gate-all-around nanowire MOSFET and method of formation K Cheng, BB Doris, P Hashemi, A Khakifirooz, A Reznicek US Patent 8,969,934, 2015 | 319 | 2015 |
| Integrated circuit having MOSFET with embedded stressor and method to fabricate same K Cheng, P Hashemi, A Khakifirooz, A Reznicek US Patent 8,975,697, 2015 | 309 | 2015 |
| Demonstration of nanosecond operation in stochastic magnetic tunnel junctions C Safranski, J Kaiser, P Trouilloud, P Hashemi, G Hu, JZ Sun Nano letters 21 (5), 2040-2045, 2021 | 128 | 2021 |
| High performance extremely thin SOI (ETSOI) hybrid CMOS with Si channel NFET and strained SiGe channel PFET K Cheng, A Khakifirooz, N Loubet, S Luning, T Nagumo, M Vinet, Q Liu, ... 2012 International Electron Devices Meeting, 18.1. 1-18.1. 4, 2012 | 126 | 2012 |
| Nanowire transistor structures with merged source/drain regions using auxiliary pillars P Hashemi, A Khakifirooz, A Reznicek US Patent 9,257,527, 2016 | 118 | 2016 |
| Stacked complementary fets featuring vertically stacked horizontal nanowires K Balakrishnan, K Cheng, P Hashemi, A Reznicek US Patent 9,837,414, 2017 | 116 | 2017 |
| Fabrication of nano-sheet transistors with different threshold voltages K Balakrishnan, K Cheng, P Hashemi, A Reznicek US Patent 9,653,289, 2017 | 97 | 2017 |
| Gate-all-around n-MOSFETs with uniaxial tensile strain-induced performance enhancement scalable to sub-10-nm nanowire diameter P Hashemi, L Gomez, JL Hoyt IEEE electron device letters 30 (4), 401-403, 2009 | 89 | 2009 |
| FINFET technology featuring high mobility SiGe channel for 10nm and beyond D Guo, G Karve, G Tsutsui, KY Lim, R Robison, T Hook, R Vega, D Liu, ... 2016 IEEE Symposium on VLSI Technology, 1-2, 2016 | 79 | 2016 |
| Contact formation to 3D monolithic stacked FinFETs K Cheng, P Hashemi, A Khakifirooz, A Reznicek US Patent 9,659,963, 2017 | 78 | 2017 |
| Vertically stacked nFET and pFET with dual work function A Reznicek, T Ando, J Zhang, CH Lee, P Hashemi US Patent 10,546,925, 2020 | 77 | 2020 |
| Vertical transistor with air gap spacers K Balakrishnan, K Cheng, P Hashemi, A Reznicek US Patent 9,443,982, 2016 | 72 | 2016 |
| Perfectly symmetric gate-all-around FET on suspended nanowire K Cheng, P Hashemi, A Khakifirooz, A Reznicek US Patent 9,853,166, 2017 | 71 | 2017 |
| Spin-transfer torque MRAM with reliable 2 ns writing for last level cache applications G Hu, JJ Nowak, MG Gottwald, SL Brown, B Doris, CP D’Emic, P Hashemi, ... 2019 IEEE International Electron Devices Meeting (IEDM), 2.6. 1-2.6. 4, 2019 | 69 | 2019 |
| Replacement III-V or germanium nanowires by unilateral confined epitaxial growth K Balakrishnan, K Cheng, P Hashemi, A Reznicek US Patent 9,570,551, 2017 | 69 | 2017 |
| Full air-gap spacers for gate-all-around nanosheet field effect transistors T Ando, P Hashemi, CH Lee, A Reznicek, J Zhang US Patent 10,553,696, 2020 | 67 | 2020 |
| Fabrication of perfectly symmetric gate-all-around FET on suspended nanowire using interface interaction K Cheng, P Hashemi, A Khakifirooz, A Reznicek US Patent 10,396,152, 2019 | 65 | 2019 |
| Formation of self-limited inner spacer for gate-all-around nanosheet FET J Zhang, T Ando, CH Lee, A Reznicek, P Hashemi US Patent 10,553,679, 2020 | 64 | 2020 |
| Channel-last replacement metal-gate vertical field effect transistor K Balakrishnan, K Cheng, P Hashemi, A Reznicek US Patent 9,525,064, 2016 | 64 | 2016 |
| Enhanced hole transport in short-channel strained-SiGe p-MOSFETs L Gomez, P Hashemi, JL Hoyt IEEE transactions on electron devices 56 (11), 2644-2651, 2009 | 64 | 2009 |
Ammar NayfehProfessor in Electrical Engineering Khalifa UniversityVerified email at ku.ac.ae
