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Nafees A. Kabir
Nafees A. Kabir
Components Research, Intel Corporation, SUNY Buffalo, Arizona State University, IIT-Kharagpur
Verified email at intel.com - Homepage
Title
Cited by
Cited by
Year
3-D self-aligned stacked NMOS-on-PMOS nanoribbon transistors for continued Moore’s law scaling
CY Huang, G Dewey, E Mannebach, A Phan, P Morrow, W Rachmady, ...
2020 IEEE International Electron Devices Meeting (IEDM), 20.6. 1-20.6. 4, 2020
1432020
Stress simulations for optimal mobility group IV p-and nMOS FinFETs for the 14 nm node and beyond
G Eneman, DP Brunco, L Witters, B Vincent, P Favia, A Hikavyy, ...
2012 International Electron Devices Meeting, 6.5. 1-6.5. 4, 2012
552012
FeRAM using anti-ferroelectric capacitors for high-speed and high-density embedded memory
SC Chang, N Haratipour, S Shivaraman, C Neumann, S Atanasov, J Peck, ...
2021 IEEE International Electron Devices Meeting (IEDM), 33.2. 1-33.2. 4, 2021
492021
Terahertz response of quantum point contacts
JW Song, NA Kabir, Y Kawano, K Ishibashi, GR Aizin, L Mourokh, ...
Applied Physics Letters 92 (22), 2008
422008
Hafnia-based FeRAM: A path toward ultra-high density for next-generation high-speed embedded memory
N Haratipour, SC Chang, S Shivaraman, C Neumann, YC Liao, ...
2022 International Electron Devices Meeting (IEDM), 6.7. 1-6.7. 4, 2022
382022
CMOS compatible process integration of SOT-MRAM with heavy-metal bi-layer bottom electrode and 10ns field-free SOT switching with STT assist
N Sato, GA Allen, WP Benson, B Buford, A Chakraborty, M Christenson, ...
2020 IEEE Symposium on VLSI Technology, 1-2, 2020
352020
Terahertz transmission characteristics of high-mobility GaAs and InAs two-dimensional-electron-gas systems
NA Kabir, Y Yoon, JR Knab, JY Chen, AG Markelz, JL Reno, Y Sadofyev, ...
Applied physics letters 89 (13), 2006
352006
Opportunities in 3-D stacked CMOS transistors
M Radosavljević, CY Huang, W Rachmady, SH Seung, NK Thomas, ...
2021 IEEE international electron devices meeting (IEDM), 34.1. 1-34.1. 4, 2021
302021
First demonstration of strained Ge-in-STI IFQW pFETs featuring raised SiGe75% S/D, replacement metal gate and germanided local interconnects
J Mitard, L Witters, B Vincent, J Franco, P Favia, A Hikavyy, G Eneman, ...
2013 Symposium on VLSI Circuits, T20-T21, 2013
192013
Subtractively patterned interconnect structures for integrated circuits
K Lin, N Sato, T TRONIC, M Christenson, C Jezewski, JR Chen, ...
US Patent 11,444,024, 2022
92022
DSA materials and processes development for≤ P24 EUV resist L/S pattern rectification
E Han, G Singh, T Mahdi, R Seidel, S Murcia, L Doyle, N Nair, N Kabir, ...
Novel Patterning Technologies 2024, PC129560P, 2024
72024
Methods and structures for improved electrical contact between bonded integrated circuit interfaces
R Vreeland, C Carver, W Brezinski, M Christenson, N KABIR
US Patent 11,289,421, 2022
72022
Planar slab vias for integrated circuit interconnects
E Karpov, M Chandhok, N KABIR
US Patent 11,239,156, 2022
62022
Reliable low-voltage FeRAM capacitors for high-speed dense embedded memory in advanced CMOS
SC Chang, C Neumann, BG Alpizar, S Atanasov, J Peck, N Kabir, YC Liao, ...
2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2024
52024
Self-aligned local interconnects
AD Lilak, E Mannebach, A Phan, R Schenker, SA BOJARSKI, ...
US Patent 11,424,160, 2022
52022
Two terminal spin orbit memory devices and methods of fabrication
N Sato, A SMITH, T Gosavi, S Manipatruni, K Oguz, K O'Brien, B Buford, ...
US Patent 11,594,673, 2023
42023
Demonstration of new planar capacitor (PCAP) vehicles to evaluate dielectrics and metal barrier thin films
KL Lin, J Bielefeld, JS Chawla, CT Carver, R Chebiam, JS Clarke, J Faber, ...
2015 IEEE International Interconnect Technology Conference and 2015 IEEE …, 2015
42015
Integrated circuit with airgaps to control capacitance
MR Reshotko, NA Kabir, M Chandhok
US Patent 10,665,499, 2020
32020
Metal spacers with hard masks formed using a subtractive process
NA Kabir, KL Lin
US Patent App. 17/579,249, 2023
22023
Subtractively patterned interconnect structures for integrated circuits
K Lin, N Sato, T TRONIC, M Christenson, C Jezewski, JR Chen, ...
US Patent 12,482,744, 2025
12025
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