| RAPL: memory power estimation and capping H David, E Gorbatov, UR Hanebutte, R Khanna, C Le Low-Power Electronics and Design (ISLPED), 2010 ACM/IEEE International …, 2010 | 820 | 2010 |
| Memory power management via dynamic voltage/frequency scaling H David, C Fallin, E Gorbatov, UR Hanebutte, O Mutlu Proceedings of the 8th ACM international conference on Autonomic computing …, 2011 | 493 | 2011 |
| Mini-rank: Adaptive DRAM architecture for improving memory power efficiency H Zheng, J Lin, Z Zhang, E Gorbatov, H David, Z Zhu Proceedings of the 41st annual IEEE/ACM International Symposium on …, 2008 | 320 | 2008 |
| Memory system with burst length shorter than prefetch length JM Dodd, HS David US Patent 6,795,899, 2004 | 155 | 2004 |
| Runnemede: An architecture for Ubiquitous High-Performance Computing NP Carter, A Agrawal, S Borkar, R Cledat, H David, D Dunning, J Fryman, ... High Performance Computer Architecture (HPCA2013), 198 - 209, 2013 | 138 | 2013 |
| System and method for thermal throttling of memory modules WR Morrow, EJ Dahlen, R Nayyar, J Dharanipathi, H David US Patent 7,318,130, 2008 | 137 | 2008 |
| Partial bank DRAM refresh H David US Patent App. 10/713,486, 2003 | 136 | 2003 |
| Two dimensional data eye centering for source synchronous data transfers JF Zumkehr, JL Bryan, HS David, K Ruff US Patent 7,036,053, 2006 | 99 | 2006 |
| Emulation of memory clock enable pin and use of chip select for memory power control H David, P Close US Patent App. 10/010,030, 2001 | 91 | 2001 |
| Thermal modeling and management of DRAM memory systems J Lin, H Zheng, Z Zhu, H David, Z Zhang ACM SIGARCH Computer Architecture News 35 (2), 312-322, 2007 | 79 | 2007 |
| Software thermal management of dram memory for multicore systems J Lin, H Zheng, Z Zhu, E Gorbatov, H David, Z Zhang ACM SIGMETRICS Performance Evaluation Review 36 (1), 337-348, 2008 | 65 | 2008 |
| Duo: Exposing on-chip redundancy to rank-level ecc for high reliability SL Gong, J Kim, S Lym, M Sullivan, H David, M Erez 2018 IEEE International Symposium on High Performance Computer Architecture …, 2018 | 56 | 2018 |
| Method of addressing individual memory devices on a memory module NS Khandekar, HS David US Patent 6,832,177, 2004 | 53 | 2004 |
| Distributed memory module cache prefetch HS David US Patent 6,925,534, 2005 | 50 | 2005 |
| Memory rank burst scheduling H Zheng, UR Hanebutte, E Gorbatov, H David US Patent 8,046,559, 2011 | 45 | 2011 |
| Segmented distributed memory module cache HS David US Patent 6,865,646, 2005 | 41 | 2005 |
| Power management using adaptive thermal throttling S Radhakrishnan, S Sah, WH Nale, R Naqib, HS David, R Agarwal US Patent 8,122,265, 2012 | 35 | 2012 |
| Asynchronous modular bus architecture with cache consistency SS Pawlowski, PD MacWilliams, DM Cowan, HS David US Patent 5,537,640, 1996 | 31 | 1996 |
| Method and apparatus for sequencing system bus grants and disabling a posting buffer in a bus bridge to improve bus efficiency HS David, MJ McTague US Patent 6,026,460, 2000 | 27 | 2000 |
| Memory power management via dynamic memory operation states HS David, UR Hanebutte, E Gorbatov, JW Alexander, S Sah US Patent 8,438,410, 2013 | 26 | 2013 |
Rahul Khanna, PhDIntel Principal EngineerVerified email at ieee.org
