| Strained Si, SiGe, and Ge channels for high-mobility metal-oxide-semiconductor field-effect transistors ML Lee, EA Fitzgerald, MT Bulsara, MT Currie, A Lochtefeld Journal of applied physics 97 (1), 2005 | 1358 | 2005 |
| Strained-semiconductor-on-insulator device structures TA Langdo, MT Currie, R Hammond, AJ Lochtefeld, EA Fitzgerald US Patent 6,995,430, 2006 | 548 | 2006 |
| Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same M Currie, A Lochtefeld, R Hammond, E Fitzgerald US Patent 6,831,292, 2004 | 514 | 2004 |
| Methods of forming strained-semiconductor-on-insulator finFET device structures AJ Lochtefeld, TA Langdo, R Hammond, MT Currie, G Braithwaite, ... US Patent 7,074,623, 2006 | 395 | 2006 |
| High quality Ge on Si by epitaxial necking TA Langdo, CW Leitz, MT Currie, EA Fitzgerald, A Lochtefeld, ... Applied Physics Letters 76 (25), 3700-3702, 2000 | 313 | 2000 |
| Defect reduction of selective Ge epitaxy in trenches on Si (001) substrates using aspect ratio trapping JS Park, J Bai, M Curtin, B Adekore, M Carroll, A Lochtefeld Applied Physics Letters 90 (5), 2007 | 280 | 2007 |
| Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication AJ Lochtefeld, MT Currie, Z Cheng, J Fiorenza, G Braithwaite, TA Langdo US Patent 8,324,660, 2012 | 248 | 2012 |
| Tri-gate field-effect transistors formed by aspect ratio trapping AJ Lochtefeld US Patent 7,799,592, 2010 | 245 | 2010 |
| Defect reduction of GaAs epitaxy on Si (001) using selective aspect ratio trapping JZ Li, J Bai, JS Park, B Adekore, K Fox, M Carroll, A Lochtefeld, ... Applied physics letters 91 (2), 2007 | 224 | 2007 |
| On experimental determination of carrier velocity in deeply scaled NMOS: How close to the thermal limit? A Lochtefeld, DA Antoniadis IEEE Electron Device Letters 22 (2), 95-97, 2002 | 220 | 2002 |
| Shallow trench isolation process MT Currie, AJ Lochtefeld US Patent 6,960,781, 2005 | 219 | 2005 |
| Defect reduction using aspect ratio trapping J Bai, JS Park, AJ Lochtefeld US Patent 8,173,551, 2012 | 211 | 2012 |
| Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication J Li, AJ Lochtefeld US Patent 9,153,645, 2015 | 175 | 2015 |
| Lattice-mismatched semiconductor structures and related methods for device fabrication AJ Lochtefeld US Patent 7,777,250, 2010 | 174 | 2010 |
| Semiconductor sensor structures with reduced dislocation defect densities Z Cheng, JG Fiorenza, C Sheen, A Lochtefeld US Patent 8,253,211, 2012 | 159 | 2012 |
| Solutions for integrated circuit integration of alternative active area materials AJ Lochtefeld, MT Currie, ZY Cheng, J Fiorenza US Patent 7,626,246, 2009 | 156 | 2009 |
| Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication AJ Lochtefeld, MT Currie, Z Cheng, J Fiorenza, G Braithwaite, TA Langdo US Patent 8,629,477, 2014 | 149 | 2014 |
| Semiconductor devices having strained dual channel layers MT Currie, AJ Lochtefeld, CW Leitz, EA Fitzgerald US Patent 7,138,310, 2006 | 149 | 2006 |
| Aspect ratio trapping for mixed signal applications A Lochtefeld, J Fiorenza US Patent App. 11/857,047, 2008 | 146 | 2008 |
| Photovoltaics on silicon J Li, AJ Lochtefeld, C Sheen, Z Cheng US Patent 9,508,890, 2016 | 145 | 2016 |
