| OTAWA: An open toolbox for adaptive WCET analysis C Ballabriga, H Cassé, C Rochange, P Sainrat IFIP International Workshop on Software Technolgies for Embedded and …, 2010 | 329 | 2010 |
| Merasa: Multicore execution of hard real-time applications supporting analyzability T Ungerer, F Cazorla, P Sainrat, G Bernat, Z Petrov, C Rochange, ... IEEE Micro 30 (5), 66-75, 2010 | 245 | 2010 |
| Papabench: a free real-time benchmark F Nemer, H Cassé, P Sainrat, JP Bahsoun, M De Michiel 6th International Workshop on Worst-Case Execution Time Analysis (WCET'06 …, 2006 | 191 | 2006 |
| Static loop bound analysis of C programs based on flow analysis and abstract interpretation M De Michiel, A Bonenfant, H Cassé, P Sainrat 2008 14th IEEE International Conference on Embedded and Real-Time Computing …, 2008 | 92 | 2008 |
| parMERASA--multi-core execution of parallelised hard real-time applications supporting analysability T Ungerer, C Bradatsch, M Gerdes, F Kluge, R Jahr, J Mische, ... 2013 Euromicro Conference on Digital System Design, 363-370, 2013 | 82 | 2013 |
| Deterministic execution model on cots hardware F Boniol, H Cassé, E Noulard, C Pagetti International Conference on Architecture of Computing Systems, 98-110, 2012 | 73 | 2012 |
| OTAWA, a framework for experimenting WCET computations H Cassé, P Sainrat Conference ERTS'06, 2006 | 68 | 2006 |
| Improving the first-miss computation in set-associative instruction caches C Ballabriga, H Cassé 2008 Euromicro Conference on Real-Time Systems, 341-350, 2008 | 58 | 2008 |
| Accurate analysis of memory latencies for WCET estimation R Bourgade, C Ballabriga, H Cassé, C Rochange, P Sainrat 16th international conference on real-time and network systems (RTNS 2008), 2008 | 44 | 2008 |
| RTOS support for parallel execution of hard real-time applications on the MERASA multi-core processor J Wolf, M Gerdes, F Kluge, S Uhrig, J Mische, S Metzlaff, C Rochange, ... 2010 13th IEEE International Symposium on Object/Component/Service-Oriented …, 2010 | 42 | 2010 |
| WCET tool challenge 2011: Report R Von Hanxleden, N Holsti, B Lisper, E Ploedereder, R Wilhelm, ... 11th International Workshop on Worst-Case Execution-Time Analysis, 2011 | 39 | 2011 |
| A versatile generator of instruction set simulators and disassemblers T Ratsiambahotra, H Cassé, P Sainrat 2009 International Symposium on Performance Evaluation of Computer …, 2009 | 30 | 2009 |
| Parallelizing industrial hard real-time applications for the parMERASA multicore T Ungerer, C Bradatsch, M Frieb, F Kluge, J Mische, A Stegmeier, R Jahr, ... ACM Transactions on Embedded Computing Systems (TECS) 15 (3), 1-27, 2016 | 28 | 2016 |
| Speculative execution and timing predictability in an open source RISC-V core A Gruin, T Carle, H Cassé, C Rochange 2021 IEEE Real-Time Systems Symposium (RTSS), 393-404, 2021 | 25 | 2021 |
| Using smt solving for the lookup of infeasible paths in binary programs J Ruiz, H Cassé 15th International Workshop on Worst-Case Execution Time Analysis (WCET 2015 …, 2015 | 19 | 2015 |
| An improved approach for set-associative instruction cache partial analysis C Ballabriga, H Cassé, P Sainrat Proceedings of the 2008 ACM symposium on Applied computing, 360-367, 2008 | 18 | 2008 |
| MINOTAuR: A timing predictable RISC-V core featuring speculative execution A Gruin, T Carle, C Rochange, H Cassé, P Sainrat IEEE Transactions on Computers 72 (1), 183-195, 2022 | 16 | 2022 |
| Reducing timing interferences in real-time applications running on multicore architectures T Carle, H Cassé 18th International Workshop on Worst-Case Execution Time Analysis (WCET 2018 …, 2018 | 16 | 2018 |
| A design flow for critical embedded systems V Lefftz, J Bertrand, H Casse, C Clienti, P Coussy, L Maillet-Contoz, ... International Symposium on Industrial Embedded System (SIES), 229-233, 2010 | 16 | 2010 |
| Improving the performance of WCET analysis in the presence of variable latencies Z Bai, H Cassé, M De Michiel, T Carle, C Rochange The 21st ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools …, 2020 | 15 | 2020 |
