| Counterexample-guided abstraction refinement E Clarke, O Grumberg, S Jha, Y Lu, H Veith International Conference on Computer Aided Verification, 154-169, 2000 | 2829 | 2000 |
| Counterexample-guided abstraction refinement for symbolic model checking E Clarke, O Grumberg, S Jha, Y Lu, H Veith Journal of the ACM (JACM) 50 (5), 752-794, 2003 | 1414 | 2003 |
| Progress on the state explosion problem in model checking E Clarke, O Grumberg, S Jha, Y Lu, H Veith Informatics: 10 Years Back, 10 Years Ahead, 176-194, 2001 | 366 | 2001 |
| Tree-like counterexamples in model checking E Clarke, S Jha, Y Lu, H Veith Proceedings 17th Annual IEEE Symposium on Logic in Computer Science, 19-29, 2002 | 198 | 2002 |
| Temporal logic for scenario-based specifications H Kugler, D Harel, A Pnueli, Y Lu, Y Bontemps International Conference on Tools and Algorithms for the Construction and …, 2005 | 144 | 2005 |
| Verifying IP-core based system-on-chip designs P Chauhan, EM Clarke, Y Lu, D Wang Twelfth Annual IEEE International ASIC/SOC Conference (Cat. No. 99TH8454), 27-31, 1999 | 90 | 1999 |
| Embedded tutorial: Formal equivalence checking between system-level models and RTL A Koelbl, Y Lu, A Mathur ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005 …, 2005 | 38 | 2005 |
| Equivalence checking using abstract BDDs S Jha, Y Lu, M Minea, EM Clarke Proceedings International Conference on Computer Design VLSI in Computers …, 1997 | 32 | 1997 |
| Executable protocol specification in ESL E Clarke, S German, Y Lu, H Veith, D Wang International Conference on Formal Methods in Computer-Aided Design, 217-236, 2000 | 23 | 2000 |
| Efficient variable ordering using aBDD based sampling Y Lu, J Jain, E Clarke, M Fujita Proceedings of the 37th Annual Design Automation Conference, 687-692, 2000 | 23 | 2000 |
| Abstract BDDs: a technique for using abstraction in model checking E Clarke, S Jha, Y Lu, D Wang Advanced Research Working Conference on Correct Hardware Design and …, 1999 | 23 | 1999 |
| Design verification using formal techniques Y Lu US Patent App. 10/835,561, 2005 | 21 | 2005 |
| OBDD variable ordering using sampling based schemes J Jain, Y Lu US Patent 6,389,374, 2002 | 21 | 2002 |
| A semi-formal verification methodology Y Lu, W Li ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No …, 2001 | 18 | 2001 |
| Automatic abstraction in model checking Y Lu Carnegie Mellon University, 2000 | 18 | 2000 |
| Synchronization of large sequential circuits by partial reset Y Lu, I Pomeranz Proceedings of 14th VLSI Test Symposium, 93-98, 1996 | 17 | 1996 |
| Methods for automatically generating assertions Y Lu, Y Zhu US Patent 7,926,020, 2011 | 13 | 2011 |
| Temporal logic for live sequence charts H Kugler, D Harel, A Pnueli, L Yuan, Y Bontemps Proc. of Tools and Algorithms for Construction and Analysis of Systems …, 2000 | 13 | 2000 |
| Systems and Methods for Generating Predicates and Assertions Y Lu, Y Zhu US Patent App. 12/634,586, 2010 | 12 | 2010 |
| Analysis of composition complexity and how to obtain smaller canonical graphs J Jain, K Mohanram, D Moundanos, I Wegener, Y Lu Proceedings of the 37th Annual Design Automation Conference, 681-686, 2000 | 10 | 2000 |
Edmund ClarkeUniversity Professor Emeritus at Carnegie Mellon UniversityVerified email at cs.cmu.edu
