| A 97.99 dB SNDR, 2 kHz BW, 37.1 µW noise-shaping SAR ADC with dynamic element matching and modulation dither effect K Obata, K Matsukawa, T Miki, Y Tsukamoto, K Sushihara 2016 IEEE symposium on VLSI circuits (VLSI-Circuits), 1-2, 2016 | 106 | 2016 |
| A 4.2 mW 50 ms/s 13 bit CMOS SAR ADC with SNR and SFDR enhancement techniques T Miki, T Morie, K Matsukawa, Y Bando, T Okumoto, K Obata, S Sakiyama, ... IEEE Journal of Solid-State Circuits 50 (6), 1372-1381, 2015 | 102 | 2015 |
| A 71dB-SNDR 50MS/s 4.2 mW CMOS SAR ADC by SNR enhancement techniques utilizing noise T Morie, T Miki, K Matsukawa, Y Bando, T Okumoto, K Obata, S Sakiyama, ... 2013 IEEE International Solid-State Circuits Conference Digest of Technical …, 2013 | 91 | 2013 |
| A 2-GS/s 8-bit time-interleaved SAR ADC for millimeter-wave pulsed radar baseband SoC T Miki, T Ozeki, J Naka IEEE Journal of Solid-State Circuits 52 (10), 2712-2720, 2017 | 78 | 2017 |
| Physical attack protection techniques for IC chip level hardware security M Nagata, T Miki, N Miura IEEE transactions on very large scale integration (VLSI) systems 30 (1), 5-14, 2021 | 62 | 2021 |
| A random interrupt dithering SAR technique for secure ADC against reference-charge side-channel attack T Miki, N Miura, H Sonoda, K Mizuta, M Nagata IEEE Transactions on Circuits and Systems II: Express Briefs 67 (1), 14-18, 2019 | 51 | 2019 |
| Si-backside protection circuits against physical security attacks on flip-chip devices T Miki, M Nagata, H Sonoda, N Miura, T Okidono, Y Araga, N Watanabe, ... IEEE Journal of Solid-State Circuits 55 (10), 2747-2755, 2020 | 45 | 2020 |
| 12.4 A 1mm-pitch 80× 80-channel 322Hz-frame-rate touch sensor with two-step dual-mode capacitance scan N Miura, S Dosho, S Takaya, D Fujimoto, T Kiriyama, H Tezuka, T Miki, ... 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014 | 40* | 2014 |
| 3-D CMOS chip stacking for security ICs featuring backside buried metal power delivery networks with distributed capacitance K Monta, H Sonoda, T Okidono, Y Araga, N Watanabe, H Shimamoto, ... IEEE Transactions on Electron Devices 68 (4), 2077-2082, 2021 | 27 | 2021 |
| An 11-b 300-MS/s double-sampling pipelined ADC with on-chip digital calibration for memory effects T Miki, T Morie, T Ozeki, S Dosho IEEE journal of solid-state circuits 47 (11), 2773-2782, 2012 | 23 | 2012 |
| AD converter including a capacitive DAC M Takuji, K Matsukawa US Patent 9,654,135, 2017 | 22 | 2017 |
| A 500MHz-BW− 52.5 dB-THD Voltage-to-Time Converter utilizing a two-step transition inverter T Miki, N Miura, K Mizuta, S Dosho, M Nagata ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 141-144, 2016 | 17 | 2016 |
| Design methods for pipeline & delta-sigma A-to-D converters with convex optimization K Matsukawa, T Morie, Y Tokunaga, S Sakiyama, Y Mitani, M Takayama, ... 2009 Asia and South Pacific Design Automation Conference, 690-695, 2009 | 17 | 2009 |
| A dual-mode successive approximation register analog to digital converter to detect malicious off-chip power noise measurement attacks T Wadatsumi, T Miki, M Nagata Japanese Journal of Applied Physics 60 (SB), SBBL03, 2021 | 14 | 2021 |
| A thick Cu layer buried in Si interposer backside for global power routing Y Araga, M Nagata, H Ikeda, T Miki, N Miura, N Watanabe, H Shimamoto, ... IEEE Transactions on Components, Packaging and Manufacturing Technology 9 (3 …, 2018 | 13 | 2018 |
| Successive approximation AD converter M Takuji, S Sakiyama, N Yanagisawa US Patent 8,947,290, 2015 | 12 | 2015 |
| An 11b 300MS/s 0.24 pJ/conversion-step double-sampling pipelined ADC with on-chip full digital calibration for all nonidealities including memory effects T Miki, T Morie, T Ozeki, S Dosho 2011 Symposium on VLSI Circuits-Digest of Technical Papers, 122-123, 2011 | 11 | 2011 |
| On-chip physical attack protection circuits for hardware security M Nagata, T Miki, N Miura 2019 IEEE Custom Integrated Circuits Conference (CICC), 1-6, 2019 | 10 | 2019 |
| A/d converter S Dosho, M Takayama US Patent 8,890,741, 2014 | 10 | 2014 |
| Time-to-digital conversion stage and time-to-digital converter including the same S Dosho, M Takuji US Patent 8,847,812, 2014 | 10 | 2014 |
