| BAG2: A process-portable framework for generator-based AMS circuit design E Chang, J Han, W Bae, Z Wang, N Narevsky, B Nikolic, E Alon 2018 IEEE Custom Integrated Circuits Conference (CICC), 1-8, 2018 | 192 | 2018 |
| A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET J Im, D Freitas, A Bantug Roldan, R Casey, S Chen, CH Adam Chou, ... IEEE Journal of Solid-State Circuits 52 (12), 3486-3502, 2017 | 143 | 2017 |
| 6.3 A 40-to-56Gb/s PAM-4 receiver with 10-tap direct decision-feedback equalization in 16nm FinFET J Im, D Freitas, A Bantug Roldan, R Casey, S Chen, CH Adam Chou, ... Solid-State Circuits Conference (ISSCC), 2017 IEEE International, 114-115, 2017 | 143* | 2017 |
| An output bandwidth optimized 200-Gb/s PAM-4 100-Gb/s NRZ transmitter with 5-tap FFE in 28-nm CMOS Z Wang, M Choi, K Lee, K Park, Z Liu, A Biswas, J Han, S Du, E Alon IEEE Journal of Solid-State Circuits 57 (1), 21-31, 2021 | 50 | 2021 |
| LAYGO: A template-and-grid-based layout generation engine for advanced CMOS technologies J Han, W Bae, E Chang, Z Wang, B Nikolić, E Alon IEEE Transactions on Circuits and Systems I: Regular Papers 68 (3), 1012-1022, 2021 | 49 | 2021 |
| Design techniques for a 60-Gb/s 288-mW NRZ transceiver with adaptive equalization and baud-rate clock and data recovery in 65-nm CMOS technology J Han, N Sutardja, Y Lu, E Alon IEEE Journal of Solid-State Circuits 52 (12), 3474-3485, 2017 | 49 | 2017 |
| Design techniques for a 60 Gb/s 173 mW wireline receiver frontend in 65 nm CMOS technology J Han, Y Lu, N Sutardja, K Jung, E Alon IEEE Journal of Solid-State Circuits 51 (4), 871-880, 2016 | 42 | 2016 |
| 8 an output-bandwidth-optimized 200Gb/s PAM-4 100Gb/s NRZ transmitter with 5-tap FFE in 28nm CMOS M Choi, Z Wang, K Lee, K Park, Z Liu, A Biswas, J Han, E Alon 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 128-130, 2021 | 41 | 2021 |
| 6.2 A 60Gb/s 288mW NRZ transceiver with adaptive equalization and baud-rate clock and data recovery in 65nm CMOS technology J Han, Y Lu, N Sutardja, E Alon 2017 IEEE International Solid-State Circuits Conference (ISSCC), 112-113, 2017 | 34 | 2017 |
| A 4.8 Gb/s impedance-matched bidirectional multi-drop transceiver for high-capacity memory interface WY Shin, GM Hong, H Lee, JD Han, S Kim, KS Park, DH Lim, JH Chun, ... 2011 IEEE International Solid-State Circuits Conference, 494-496, 2011 | 32 | 2011 |
| A mixed-signal risc-v signal analysis soc generator with a 16-nm finfet instance S Bailey, P Rigge, J Han, R Lin, EY Chang, H Mao, Z Wang, C Markley, ... IEEE Journal of Solid-State Circuits 54 (10), 2786-2801, 2019 | 27 | 2019 |
| A supply-scalable-serializing transmitter with controllable output swing and equalization for next-generation standards W Bae, H Ju, K Park, J Han, DK Jeong IEEE Transactions on Industrial Electronics 65 (7), 5979-5989, 2017 | 20 | 2017 |
| A 60Gb/s 173mW receiver frontend in 65nm CMOS technology J Han, Y Lu, N Sutardja, K Jung, E Alon 2015 Symposium on VLSI Circuits (VLSI Circuits), C230-C231, 2015 | 20 | 2015 |
| 6.8 A 100Gb/s 1.6Vppd PAM-8 Transmitter with High-Swing Hybrid FFE Taps in 40nm J Yang, E Song, S Hong, D Lee, S Lee, H Im, T Shin, J Han 2023 IEEE International Solid-State Circuits Conference (ISSCC), 122-124, 2023 | 18 | 2023 |
| LAYGO2: A custom layout generation engine based on dynamic templates and grids for advanced CMOS technologies T Shin, D Lee, D Kim, G Sung, W Shin, Y Jo, H Park, J Han IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2023 | 17 | 2023 |
| An automated SerDes frontend generator verified with a 16-nm instance achieving 15 Gb/s at 1.96 pJ/bit E Chang, N Narevsky, J Han, E Alon IEEE Solid-State Circuits Letters 1 (12), 245-248, 2019 | 14 | 2019 |
| A 1.5-GS/s 6-bit single-channel loop-unrolled SAR ADC with speculative CDAC switching control technique in 28-nm CMOS E Lee, C Pyo, S Lee, J Han IEEE Transactions on Circuits and Systems I: Regular Papers 69 (10), 3954-3964, 2022 | 13 | 2022 |
| A real-time, 1.89-GHz bandwidth, 175-kHz resolution sparse spectral analysis RISC-V SoC in 16-nm FinFET A Wang, W Bae, J Han, S Bailey, O Ocal, P Rigge, Z Wang, ... IEEE Journal of Solid-State Circuits 54 (7), 1993-2008, 2019 | 13 | 2019 |
| 4-slot, 8-drop impedance-matched bidirectional multidrop DQ bus with a 4.8-Gb/s memory controller transceiver WY Shin, GM Hong, H Lee, JD Han, KS Park, DH Lim, S Kim, D Shim, ... IEEE Transactions on Components, Packaging and Manufacturing Technology 3 (5 …, 2013 | 11 | 2013 |
| Precursor ISI cancellation sliding-block DFE for high-speed wireline receivers K Kim, S Moon, J Han, E Alon, AM Niknejad IEEE Transactions on Circuits and Systems I: Regular Papers 70 (10), 4169-4182, 2023 | 10 | 2023 |
Woorham BaeAyar LabsVerified email at ayarlabs.com
