| A 2.6 nW, 0.45 V temperature-compensated subthreshold CMOS voltage reference L Magnelli, F Crupi, P Corsonello, C Pace, G Iannaccone IEEE Journal of Solid-State Circuits 46 (2), 465-474, 2010 | 370 | 2010 |
| Low-power level shifter for multi-supply voltage designs M Lanuzza, P Corsonello, S Perri IEEE Transactions on Circuits and Systems II: Express Briefs 59 (12), 922-926, 2012 | 159 | 2012 |
| Fast and wide range voltage conversion in multisupply voltage designs M Lanuzza, P Corsonello, S Perri IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (2), 388-391, 2014 | 125 | 2014 |
| Area-delay efficient binary adders in QCA S Perri, P Corsonello, G Cocorullo IEEE transactions on very large scale integration (vlsi) systems 22 (5 …, 2013 | 103 | 2013 |
| New methodology for the design of efficient binary addition circuits in QCA S Perri, P Corsonello IEEE transactions on nanotechnology 11 (6), 1192-1200, 2012 | 88 | 2012 |
| Compressed sensing approach for physiological signals: A review B Lal, R Gravina, F Spagnolo, P Corsonello IEEE Sensors Journal 23 (6), 5513-5534, 2023 | 74 | 2023 |
| A high-performance fully reconfigurable FPGA-based 2D convolution processor S Perri, M Lanuzza, P Corsonello, G Cocorullo Microprocessors and Microsystems 29 (8-9), 381-391, 2005 | 68 | 2005 |
| A high-speed FPGA-based true random number generator using metastability with clock managers F Frustaci, F Spagnolo, S Perri, P Corsonello IEEE Transactions on Circuits and Systems II: Express Briefs 70 (2), 756-760, 2022 | 67 | 2022 |
| Fast low-cost implementation of single-clock-cycle binary comparator S Perri, P Corsonello IEEE Transactions on Circuits and Systems II: Express Briefs 55 (12), 1239-1243, 2008 | 67 | 2008 |
| Analytical delay model considering variability effects in subthreshold domain F Frustaci, P Corsonello, S Perri IEEE Transactions on Circuits and Systems II: Express Briefs 59 (3), 168-172, 2012 | 64 | 2012 |
| Gate‐level body biasing technique for high‐speed sub‐threshold CMOS logic gates P Corsonello, M Lanuzza, S Perri International journal of circuit theory and applications 42 (1), 65-70, 2014 | 63 | 2014 |
| SAD-based stereo matching circuit for FPGAs S Perri, D Colonna, P Zicari, P Corsonello 2006 13th IEEE International Conference on Electronics, Circuits and Systems …, 2006 | 61 | 2006 |
| Design of efficient BCD adders in quantum-dot cellular automata G Cocorullo, P Corsonello, F Frustaci, S Perri IEEE Transactions on Circuits and Systems II: Express Briefs 64 (5), 575-579, 2016 | 56 | 2016 |
| Adaptive Census Transform: A novel hardware-oriented stereovision algorithm S Perri, P Corsonello, G Cocorullo Computer Vision and Image Understanding 117 (1), 29-41, 2013 | 56 | 2013 |
| An embedded machine vision system for an in-line quality check of assembly processes F Frustaci, S Perri, G Cocorullo, P Corsonello Procedia Manufacturing 42, 211-218, 2020 | 55 | 2020 |
| A new reconfigurable coarse-grain architecture for multimedia applications M Lanuzza, S Perri, P Corsonello, M Margala Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 119-126, 2007 | 55 | 2007 |
| Design of efficient binary comparators in quantum-dot cellular automata S Perri, P Corsonello, G Cocorullo IEEE transactions on nanotechnology 13 (2), 192-202, 2013 | 51 | 2013 |
| Low-power split-path data-driven dynamic logic F Frustaci, M Lanuzza, P Zicari, S Perri, P Corsonello IET circuits, devices & systems 3 (6), 303-312, 2009 | 50 | 2009 |
| Designing high-speed adders in power-constrained environments F Frustaci, M Lanuzza, P Zicari, S Perri, P Corsonello IEEE Transactions on Circuits and Systems II: Express Briefs 56 (2), 172-176, 2009 | 45 | 2009 |
| Low bit rate image compression core for onboard space applications P Corsonello, S Perri, G Staino, M Lanuzza, G Cocorullo Circuits and Systems for Video Technology, IEEE Transactions on 16 (1), 114-128, 2006 | 45 | 2006 |
