| Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET N Loubet, T Hook, P Montanini, CW Yeung, S Kanakasabapathy, ... 2017 symposium on VLSI technology, T230-T231, 2017 | 1270 | 2017 |
| A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels R Xie, P Montanini, K Akarvardar, N Tripathi, B Haran, S Johnson, T Hook, ... 2016 IEEE international electron devices meeting (IEDM), 2.7. 1-2.7. 4, 2016 | 207 | 2016 |
| Method of assessing potential for charging damage in SOI designs and structures for eliminating potential for damage HA Bonges III, DL Harmon, TB Hook, WL Lai US Patent 7,067,886, 2006 | 168 | 2006 |
| Performance trade-offs in FinFET and gate-all-around device architectures for 7nm-node and beyond SD Kim, M Guillorn, I Lauer, P Oldiges, T Hook, MH Na 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference …, 2015 | 164 | 2015 |
| Lateral ion implant straggle and mask proximity effect TB Hook, J Brown, P Cottrell, E Adler, D Hoyniak, J Johnson, R Mann IEEE Transactions on Electron Devices 50 (9), 1946-1951, 2003 | 142 | 2003 |
| High speed 45nm gate length CMOSFETs integrated into a 90nm bulk technology incorporating strain engineering V Chan, R Rengarajan, N Rovedo, W Jin, T Hook, P Nguyen, J Chen, ... IEEE International Electron Devices Meeting 2003, 3.8. 1-3.8. 4, 2003 | 122 | 2003 |
| A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI KI Seo, B Haran, D Gupta, D Guo, T Standaert, R Xie, H Shang, E Alptekin, ... 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical …, 2014 | 112 | 2014 |
| The effects of Fluorine on parametrics and reliability in a 0.18-/spl mu/m 3.5/6.8 nm dual gate oxide CMOS technology TB Hook, E Adler, F Guarin, J Lukaitis, N Rovedo, K Schruefer IEEE Transactions on Electron Devices 48 (7), 1346-1353, 2001 | 111 | 2001 |
| High performance and low power transistors integrated in 65nm bulk CMOS technology Z Luo, A Steegen, M Eller, R Mann, C Baiocco, P Nguyen, L Kim, ... IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004 …, 2004 | 108 | 2004 |
| Use of deuterated materials in semiconductor processing WF Clark, TG Ference, TB Hook, DW Martin US Patent 5,972,765, 1999 | 107 | 1999 |
| CMOS well structure and method of forming the same W Haensch, TB Hook, LC Hsu, RV Joshi, W Rausch US Patent 7,132,323, 2006 | 103 | 2006 |
| Switching-speed limitations of ferroelectric negative-capacitance FETs ZC Yuan, S Rizwan, M Wong, K Holland, S Anderson, TB Hook, D Kienle, ... IEEE Transactions on Electron Devices 63 (10), 4046-4052, 2016 | 100 | 2016 |
| Enchanced multi-threshold (MTCMOS) circuits using variable well bias SV Kosonocky, M Immediato, P Cottrell, T Hook, R Mann, J Brown Proceedings of the 2001 international symposium on Low power electronics and …, 2001 | 98 | 2001 |
| Channel doping impact on FinFETs for 22nm and beyond CH Lin, R Kambhampati, RJ Miller, TB Hook, A Bryant, W Haensch, ... 2012 Symposium on VLSI Technology (VLSIT), 15-16, 2012 | 92 | 2012 |
| Physically unclonable function implemented through threshold voltage comparison JT Ficke, WE Hall, TB Hook, MA Sperling, L Wissel US Patent 8,619,979, 2013 | 91 | 2013 |
| FINFET technology featuring high mobility SiGe channel for 10nm and beyond D Guo, G Karve, G Tsutsui, KY Lim, R Robison, T Hook, R Vega, D Liu, ... 2016 IEEE Symposium on VLSI Technology, 1-2, 2016 | 79 | 2016 |
| Mechanism of threshold voltage shift (ΔVth) caused by negative bias temperature instability (NBTI) in deep submicron pMOSFETs CH Liu, MT Lee, CY Lin, J Chen, YT Loh, FT Liou, K Schruefer, ... Japanese journal of applied physics 41 (4S), 2423, 2002 | 74 | 2002 |
| Impact of back bias on ultra-thin body and BOX (UTBB) devices Q Liu, F Monsieur, A Kumar, T Yamamoto, A Yagishita, P Kulkarni, ... 2011 Symposium on VLSI Technology-Digest of Technical Papers, 160-161, 2011 | 70 | 2011 |
| Evaluation of 10-nm bulk FinFET RF performance—Conventional versus NC-FinFET R Singh, K Aditya, SS Parihar, YS Chauhan, R Vega, TB Hook, A Dixit IEEE Electron Device Letters 39 (8), 1246-1249, 2018 | 69 | 2018 |
| Gate-induced-drain-leakage current in 45-nm CMOS technology X Yuan, JE Park, J Wang, E Zhao, DC Ahlgren, T Hook, J Yuan, ... IEEE Transactions on Device and Materials Reliability 8 (3), 501-508, 2008 | 69 | 2008 |
