| Low-latency virtual-channel routers for on-chip networks R Mullins, A West, S Moore ACM SIGARCH Computer Architecture News 32 (2), 188, 2004 | 649 | 2004 |
| Efficient physical embedding of topologically complex information processing networks in brains and computer circuits DS Bassett, DL Greenfield, A Meyer-Lindenberg, DR Weinberger, ... PLoS computational biology 6 (4), e1000748, 2010 | 505 | 2010 |
| The CHERI capability model: Revisiting RISC in an age of risk J Woodruff, RNM Watson, D Chisnall, SW Moore, J Anderson, B Davis, ... ACM SIGARCH Computer Architecture News 42 (3), 457-468, 2014 | 494 | 2014 |
| CHERI: A hybrid capability-system architecture for scalable software compartmentalization RNM Watson, J Woodruff, PG Neumann, SW Moore, J Anderson, ... 2015 IEEE Symposium on Security and Privacy, 20-37, 2015 | 472 | 2015 |
| Improving smart card security using self-timed circuits S Moore, R Anderson, P Cunningham, R Mullins, G Taylor Proceedings Eighth International Symposium on Asynchronous Circuits and …, 2002 | 284 | 2002 |
| The frequency injection attack on ring-oscillator-based true random number generators AT Markettos, SW Moore International Workshop on Cryptographic Hardware and Embedded Systems, 317-331, 2009 | 272 | 2009 |
| A communication characterisation of splash-2 and parsec N Barrow-Williams, C Fensch, S Moore 2009 IEEE international symposium on workload characterization (IISWC), 86-97, 2009 | 264 | 2009 |
| Point to point GALS interconnect S Moore, G Taylor, R Mullins, P Robinson Proceedings Eighth International Symposium on Asynchronous Circuits and …, 2002 | 194 | 2002 |
| Capability hardware enhanced RISC instructions: CHERI instruction-set architecture (version 7) RNM Watson, PG Neumann, J Woodruff, M Roe, H Almatary, J Anderson, ... University of Cambridge, Computer Laboratory, 2019 | 174 | 2019 |
| The design and implementation of a low-latency on-chip network R Mullins, A West, S Moore Proceedings of the 2006 Asia and South Pacific Design Automation Conference …, 2006 | 173 | 2006 |
| Bluehive-a field-programable custom computing machine for extreme-scale real-time neural network simulation SW Moore, PJ Fox, SJT Marsh, AT Markettos, A Mujumdar 2012 IEEE 20th International Symposium on Field-Programmable Custom …, 2012 | 158 | 2012 |
| A power and energy exploration of network-on-chip architectures A Banerjee, R Mullins, S Moore First International Symposium on Networks-on-Chip (NOCS'07), 163-172, 2007 | 150 | 2007 |
| Balanced self-checking asynchronous logic for smart card applications S Moore, R Anderson, R Mullins, G Taylor, JJA Fournier Microprocessors and Microsystems 27 (9), 421-430, 2003 | 142 | 2003 |
| Thunderclap: Exploring vulnerabilities in operating system IOMMU protection via DMA from untrustworthy peripherals AT Markettos, C Rothwell, BF Gutstein, A Pearce, PG Neumann, ... Internet Society, 2019 | 132 | 2019 |
| Security evaluation of asynchronous circuits JJA Fournier, S Moore, H Li, R Mullins, G Taylor International Workshop on Cryptographic Hardware and Embedded Systems, 137-151, 2003 | 128 | 2003 |
| Beyond the PDP-11: Architectural support for a memory-safe C abstract machine D Chisnall, C Rothwell, RNM Watson, J Woodruff, M Vadera, SW Moore, ... ACM SIGARCH Computer Architecture News 43 (1), 117-130, 2015 | 122 | 2015 |
| Cornucopia: Temporal safety for CHERI heaps NW Filardo, BF Gutstein, J Woodruff, S Ainsworth, L Paul-Trifu, B Davis, ... 2020 IEEE Symposium on Security and Privacy (SP), 608-625, 2020 | 111 | 2020 |
| Cherivoke: Characterising pointer revocation using cheri capabilities for temporal memory safety H Xia, J Woodruff, S Ainsworth, NW Filardo, M Roe, A Richardson, ... Proceedings of the 52nd Annual IEEE/ACM International Symposium on …, 2019 | 111 | 2019 |
| CheriABI: Enforcing valid pointer provenance and minimizing pointer privilege in the POSIX C run-time environment B Davis, RNM Watson, A Richardson, PG Neumann, SW Moore, ... Proceedings of the Twenty-Fourth International Conference on Architectural …, 2019 | 105 | 2019 |
| Demystifying data-driven and pausible clocking schemes R Mullins, S Moore 13th IEEE International Symposium on Asynchronous Circuits and Systems …, 2007 | 103 | 2007 |
Robert N. M. WatsonDepartment of Computer Science and Technology, University of CambridgeVerified email at cl.cam.ac.uk
