| Inference and abstraction of the biometric passport F Aarts, J Schmaltz, F Vaandrager International Symposium On Leveraging Applications of Formal Methods …, 2010 | 117 | 2010 |
| On conformance testing for timed systems J Schmaltz, J Tretmans International Conference on Formal Modeling and Analysis of Timed Systems …, 2008 | 96 | 2008 |
| Analysis of a clock synchronization protocol for wireless sensor networks F Heidarian, J Schmaltz, F Vaandrager International Symposium on Formal Methods, 516-531, 2009 | 80 | 2009 |
| A generic model for formally verifying NoC communication architectures: A case study D Borrione, A Helmy, L Pierre, J Schmaltz First International Symposium on Networks-on-Chip (NOCS'07), 127-136, 2007 | 51 | 2007 |
| Formal API specification of the PikeOS separation kernel F Verbeek, O Havle, J Schmaltz, S Tverdyshev, H Blasum, B Langenstein, ... NASA formal methods symposium, 375-389, 2015 | 44 | 2015 |
| A decision procedure for deadlock-free routing in wormhole networks F Verbeek, J Schmaltz IEEE transactions on parallel and distributed systems 25 (8), 1935-1944, 2013 | 41* | 2013 |
| A formal approach to the verification of networks on chip D Borrione, A Helmy, L Pierre, J Schmaltz EURASIP Journal on Embedded Systems 2009 (1), 548324, 2009 | 39 | 2009 |
| A functional formalization of on chip communications J Schmaltz, D Borrione Formal Aspects of Computing 20 (3), 241-258, 2008 | 39* | 2008 |
| Hunting deadlocks efficiently in microarchitectural models of communication fabrics F Verbeek, J Schmaltz 2011 Formal Methods in Computer-Aided Design (FMCAD), 223-231, 2011 | 37 | 2011 |
| On necessary and sufficient conditions for deadlock-free routing in wormhole networks F Verbeek, J Schmaltz IEEE Transactions on Parallel and Distributed Systems 22 (12), 2022-2032, 2011 | 36 | 2011 |
| Model-based testing of electronic passports WI Mostowski, E Poll, J Schmaltz, J Tretmans, RJM Wichers Schreur Berlin: Springer Verlag, 2009 | 36 | 2009 |
| A formal model of clock domain crossing and automated verification of time-triggered hardware J Schmaltz Formal Methods in Computer Aided Design, 2007. FMCAD'07, 223-230, 2007 | 35* | 2007 |
| A functional approach to the formal specification of networks on chip J Schmaltz, D Borrione Formal Methods in Computer-Aided Design, 52-66, 2004 | 28 | 2004 |
| Towards a formal theory of on chip communications in the ACL2 logic J Schmaltz, D Borrione Proceedings of the sixth international workshop on the ACL2 theorem prover …, 2006 | 27 | 2006 |
| A generic network on chip model J Schmaltz, D Borrione International Conference on Theorem Proving in Higher Order Logics, 310-325, 2005 | 27 | 2005 |
| A conformance testing relation for symbolic timed automata S Von Styp, H Bohnenkamp, J Schmaltz International Conference on Formal Modeling and Analysis of Timed Systems …, 2010 | 25 | 2010 |
| Formal specification of networks-on-chips: deadlock and evacuation F Verbeek, J Schmaltz 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010 | 25 | 2010 |
| Logic Gates, Circuits, Processors, Compilers and Computers JF Groote, R Morel, J Schmaltz, A Watkins Springer International Publishing, 2021 | 21 | 2021 |
| The axiomatization of override and update J Berendsen, DN Jansen, J Schmaltz, FW Vaandrager Journal of Applied Logic 8 (1), 141-150, 2010 | 21 | 2010 |
| A comment on "A Necessary and Sufficient Condition for Deadlock-Free Adaptive Routing in Wormhole Networks” F Verbeek, J Schmaltz Parallel and Distributed Systems, IEEE Transactions on 22 (10), 1775-1776, 2011 | 18 | 2011 |
Freek VerbeekRadboud University, The NetherlandsVerified email at ou.nl
