| Power-management architecture of the intel microarchitecture code-named sandy bridge E Rotem, A Naveh, A Ananthakrishnan, E Weissmann, D Rajwan Ieee micro 32 (2), 20-27, 2012 | 657 | 2012 |
| Inside 6th-generation intel core: New microarchitecture code-named skylake J Doweck, WF Kao, AK Lu, J Mandelblat, A Rahatekar, L Rappoport, ... IEEE Micro 37 (2), 52-62, 2017 | 246 | 2017 |
| Method and apparatus to control power consumption of a plurality of processor cores E Rotem, O Lamdan, A Naveh US Patent 8,650,424, 2014 | 216 | 2014 |
| Power and Thermal Management in the Intel Core Duo Processor. A Naveh, E Rotem, A Mendelson, S Gochman, R Chabukswar, ... Intel Technology Journal 10 (2), 2006 | 200 | 2006 |
| Dynamically allocating a power budget over multiple domains of a processor AN Ananthakrishnan, E Rotem, D Rajwan, E Weissmann, N Shulman US Patent 8,769,316, 2014 | 197 | 2014 |
| Power management coordination in multi-core processors A Naveh, E Rotem, E Weissmann US Patent 7,966,511, 2011 | 173 | 2011 |
| Controlling a turbo mode frequency of a processor AN Ananthakrishnan, E Rotem, D Rajwan, E Wiessman, R Wells, ... US Patent 8,943,340, 2015 | 171 | 2015 |
| Dynamically controlling cache size to maximize energy efficiency AN Ananthakrishnan, E Rotem, E Weissmann, D Rajwan, N Shulman, ... US Patent 9,158,693, 2015 | 169 | 2015 |
| Controlling operating frequency of a core domain via a non-core domain of a multi-domain processor AN Ananthakrishnan, E Rotem, D Rajwan, JJ Shrall, EC Samson, ... US Patent 9,026,815, 2015 | 152 | 2015 |
| Controlling temperature of multiple domains of a multi-domain processor using a cross domain margin AN Ananthakrishan, T Ziv, D Rajwan, E Rotem US Patent 8,954,770, 2015 | 152 | 2015 |
| Enabling a non-core domain to control memory bandwidth in a processor AN Ananthakrishnan, IM Sodhi, E Rotem, D Rajwan, E Wiessman, ... US Patent 8,832,478, 2014 | 152 | 2014 |
| Estimating temperature of a processor core in a low power state without thermal sensor information AN Ananthakrishnan, E Rotem, I Feit, T Ziv, D Rajwan, N Shulman, ... US Patent 9,074,947, 2015 | 145 | 2015 |
| Power management architecture of the 2nd generation Intel® Core microarchitecture, formerly codenamed Sandy Bridge E Rotem, A Naveh, D Rajwan, A Ananthakrishnan, E Weissmann 2011 IEEE Hot Chips 23 Symposium (HCS), 1-33, 2011 | 128 | 2011 |
| Method, system, and apparatus for selecting a maximum operation point based on number of active cores and performance level of each of the active cores E Rotem, O Lamdan, A Naveh US Patent 7,502,948, 2009 | 119 | 2009 |
| Introduction to intel core duo processor architecture. S Gochman, A Mendelson, A Naveh, E Rotem Intel Technology Journal 10 (2), 2006 | 119 | 2006 |
| Temperature measurement in the intel (R) coretm duo processor E Rotem, J Hermerding, A Cohen, H Cain arXiv preprint arXiv:0709.1861, 2007 | 94 | 2007 |
| Power management for multiple processor cores L Finkelstein, E Rotem, A Cohen, R Ronen, D Rajwan US Patent 8,402,290, 2013 | 77 | 2013 |
| Controlling operation of a voltage supply according to the activity of a multi-core integrated circuit component or of multiple IC components E Rotem US Patent App. 10/442,595, 2005 | 72 | 2005 |
| Multiple clock and voltage domains for chip multi processors E Rotem, A Mendelson, R Ginosar, U Weiser Proceedings of the 42nd Annual IEEE/ACM International Symposium on …, 2009 | 68 | 2009 |
| Intel alder lake cpu architectures E Rotem, A Yoaz, L Rappoport, SJ Robinson, JY Mandelblat, A Gihon, ... IEEE Micro 42 (3), 13-19, 2022 | 67 | 2022 |
Nir RosenzweigVerified email at nvidia.com
