| A survey and comparative study of hard and soft real-time dynamic resource allocation strategies for multi-/many-core systems AK Singh, P Dziurzanski, HR Mendis, LS Indrusiak ACM Computing Surveys (CSUR) 50 (2), 1-40, 2017 | 119 | 2017 |
| End-to-end schedulability tests for multiprocessor embedded systems based on networks-on-chip with priority-preemptive arbitration LS Indrusiak Journal of systems architecture 60 (7), 553-561, 2014 | 98 | 2014 |
| A generic and compositional framework for multicore response time analysis S Altmeyer, RI Davis, L Indrusiak, C Maiza, V Nelis, J Reineke Proceedings of the 23rd International Conference on Real Time and Networks …, 2015 | 94 | 2015 |
| A wormhole noc protocol for mixed criticality systems A Burns, J Harbin, LS Indrusiak 2014 IEEE Real-Time Systems Symposium, 184-195, 2014 | 91 | 2014 |
| Schedulability analysis for real time on-chip communication with wormhole switching Z Shi, A Burns, LS Indrusiak Innovations in embedded and real-time systems engineering for communication …, 2012 | 84 | 2012 |
| An extensible framework for multicore response time analysis RI Davis, S Altmeyer, LS Indrusiak, C Maiza, V Nelis, J Reineke Real-Time Systems 54 (3), 607-661, 2018 | 74 | 2018 |
| Latency and lifetime enhancements in industrial wireless sensor networks: A Q-learning approach for graph routing G Künzel, LS Indrusiak, CE Pereira IEEE Transactions on Industrial Informatics 16 (8), 5617-5625, 2019 | 63 | 2019 |
| Real-time low-power task mapping in networks-on-chip MNSM Sayuti, LS Indrusiak 2013 IEEE computer society annual symposium on VLSI (ISVLSI), 14-19, 2013 | 60 | 2013 |
| Power-aware dynamic mapping heuristics for NoC-based MPSoCs using a unified model-based approach L Ost, M Mandelli, GM Almeida, L Moller, LS Indrusiak, G Sassatelli, ... ACM Transactions on Embedded Computing Systems (TECS) 12 (3), 1-22, 2013 | 54 | 2013 |
| Using genetic algorithms to map hard real-time on noc-based systems A Racu, LS Indrusiak 7th International Workshop on Reconfigurable and Communication-Centric …, 2012 | 54 | 2012 |
| Average and worst-case latency improvements in mixed-criticality wormhole networks-on-chip LS Indrusiak, J Harbin, A Burns 2015 27th Euromicro Conference on Real-Time Systems, 47-56, 2015 | 53 | 2015 |
| Genetic mapping of hard real-time applications onto NoC-based MPSoCs—A first approach P Mesidis, LS Indrusiak 6th International workshop on reconfigurable communication-centric systems …, 2011 | 51 | 2011 |
| On the evolution of remote laboratories for prototyping digital electronic systems LS Indrusiak, M Glesner, R Reis IEEE Transactions on Industrial Electronics 54 (6), 3069-3077, 2007 | 50 | 2007 |
| A survey of scheduling metrics and an improved ordering policy for list schedulers operating on workloads with dependencies and a wide variation in execution times A Burkimsher, I Bate, LS Indrusiak Future Generation Computer Systems 29 (8), 2009-2025, 2013 | 46 | 2013 |
| MADES FP7 EU project: Effective high level SysML/MARTE methodology for real-time and embedded avionics systems IR Quadri, E Brosse, I Gray, N Matragkas, LS Indrusiak, M Rossi, ... 7th International Workshop on Reconfigurable and Communication-Centric …, 2012 | 45 | 2012 |
| Exploring NoC-Based MPSoC Design Space with Power Estimation Models L Ost, G Guindani, F Moraes, L Indrusiak, S Maatta IEEE Design & Test 28 (2), 16-29, 2011 | 40* | 2011 |
| Side-channel attack resilience through route randomisation in secure real-time networks-on-chip LS Indrusiak, J Harbin, MJ Sepulveda 2017 12th International Symposium on Reconfigurable Communication-centric …, 2017 | 35 | 2017 |
| Real-time analysis of priority-preemptive NoCs with arbitrary buffer sizes and router delays B Nikolić, S Tobuschat, L Soares Indrusiak, R Ernst, A Burns Real-Time Systems 55 (1), 63-105, 2019 | 34 | 2019 |
| Buffer-aware bounds to multi-point progressive blocking in priority-preemptive NoCs LS Indrusiak, A Burns, B Nikolić 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 219-224, 2018 | 33 | 2018 |
| 3D integrated circuit layout visualization using VRML LS Indrusiak, RA da Luz Reis Future Generation Computer Systems 17 (5), 503-511, 2001 | 33 | 2001 |
Ricardo Augusto da Luz ReisUFRGSVerified email at inf.ufrgs.br
