| In-memory computing: Advances and prospects N Verma, H Jia, H Valavi, Y Tang, M Ozatay, LY Chen, B Zhang, ... IEEE solid-state circuits magazine 11 (3), 43-55, 2019 | 542 | 2019 |
| A programmable heterogeneous microprocessor based on bit-scalable in-memory computing H Jia, H Valavi, Y Tang, J Zhang, N Verma IEEE Journal of Solid-State Circuits 55 (9), 2609-2621, 2020 | 263 | 2020 |
| 15.1 a programmable neural-network inference accelerator based on scalable in-memory computing H Jia, M Ozatay, Y Tang, H Valavi, R Pathak, J Lee, N Verma 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 236-238, 2021 | 191* | 2021 |
| Scalable and programmable neural network inference accelerator based on in-memory computing H Jia, M Ozatay, Y Tang, H Valavi, R Pathak, J Lee, N Verma IEEE Journal of Solid-State Circuits 57 (1), 198-211, 2021 | 135 | 2021 |
| 7.3 A 28nm 38-to-102-TOPS/W 8b multiply-less approximate digital SRAM compute-in-memory macro for neural-network inference Y He, H Diao, C Tang, W Jia, X Tang, Y Wang, J Yue, X Li, H Yang, H Jia, ... 2023 IEEE International Solid-State Circuits Conference (ISSCC), 130-132, 2023 | 52 | 2023 |
| A microprocessor implemented in 65nm CMOS with configurable and bit-scalable accelerator for programmable in-memory computing H Jia, Y Tang, H Valavi, J Zhang, N Verma arXiv preprint arXiv:1811.04047, 2018 | 49 | 2018 |
| 34.7 A 28nm 2.4Mb/mm2 6.9 - 16.3TOPS/mm2 eDRAM-LUT-Based Digital-Computing-in-Memory Macro with In-Memory Encoding and Refreshing Y He, S Fan, X Li, L Lei, W Jia, C Tang, Y Li, Z Huang, Z Du, J Yue, X Li, ... 2024 IEEE International Solid-State Circuits Conference (ISSCC) 67, 578-580, 2024 | 36 | 2024 |
| An RRAM-based digital computing-in-memory macro with dynamic voltage sense amplifier and sparse-aware approximate adder tree Y He, J Yue, X Feng, Y Huang, H Jia, J Wang, L Zhang, W Sun, H Yang, ... IEEE Transactions on Circuits and Systems II: Express Briefs 70 (2), 416-420, 2022 | 33 | 2022 |
| A survey of computing-in-memory processor: From circuit to application W Sun, J Yue, Y He, Z Huang, J Wang, W Jia, Y Li, L Lei, H Jia, Y Liu IEEE Open Journal of the Solid-State Circuits Society 4, 25-42, 2023 | 29 | 2023 |
| A phased array based on large-area electronics that operates at gigahertz frequency C Wu, Y Mehlman, P Kumar, T Moy, H Jia, Y Ma, S Wagner, JC Sturm, ... Nature Electronics 4 (10), 757-766, 2021 | 26 | 2021 |
| Configurable in memory computing engine, platform, bit cells and layouts therefore N Verma, H VALAVI, H Jia US Patent 11,669,446, 2023 | 24 | 2023 |
| Cramming More Weight Data Onto Compute-in-Memory Macros for High Task-Level Energy Efficiency Using Custom ROM With 3984-kb/mm2 Density in 65-nm … G Yin, Y Chen, M Zhou, W Tang, M Lee, Z Yang, T Liao, X Du, ... IEEE Journal of Solid-State Circuits 59 (6), 1912-1925, 2023 | 19 | 2023 |
| Genetic programming for energy-efficient and energy-scalable approximate feature computation in embedded inference systems J Lu, H Jia, N Verma, NK Jha IEEE Transactions on Computers 67 (2), 222-236, 2017 | 17 | 2017 |
| Artificial intelligence meets large-scale sensing: Using large-area electronics (LAE) to enable intelligent spaces M Ozatay, L Aygun, H Jia, P Kumar, Y Mehlman, C Wu, S Wagner, ... 2018 IEEE Custom Integrated Circuits Conference (CICC), 1-8, 2018 | 16 | 2018 |
| Exploiting approximate feature extraction via genetic programming for hardware acceleration in a heterogeneous microprocessor H Jia, N Verma IEEE Journal of Solid-State Circuits 53 (4), 1016-1027, 2018 | 15 | 2018 |
| A Programmable Embedded Microprocessor for Bit-scalable In-memory Computing. H Jia, H Valavi, Y Tang, J Zhang, N Verma Hot Chips Symposium, 1-29, 2019 | 14 | 2019 |
| A multiply-less approximate sram compute-in-memory macro for neural-network inference H Diao, Y He, X Li, C Tang, W Jia, J Yue, H Luo, J Song, X Li, H Yang, ... IEEE Journal of Solid-State Circuits, 2024 | 13 | 2024 |
| Scalable array architecture for in-memory computing H Jia, M OZATAY, H VALAVI, N Verma US Patent App. 17/797,833, 2023 | 11 | 2023 |
| A 28nm 8928Kb/mm2-Weight-Density Hybrid SRAM/ROM Compute-in-Memory Architecture Reducing >95% Weight Loading from DRAM G Yin, Y Chen, M Lee, X Du, Y Ke, W Tang, Z Chen, M Zhou, J Yue, ... 2024 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2024 | 10 | 2024 |
| A heterogeneous microprocessor based on all-digital compute-in-memory for end-to-end AIoT inference S Yu, Y He, H Jia, W Sun, M Zhou, L Lei, W Zhao, G Ma, H Yang, Y Liu IEEE Transactions on Circuits and Systems II: Express Briefs 70 (8), 3099-3103, 2023 | 10 | 2023 |
