| High-Speed NTT-based Polynomial Multiplication Accelerator for Post-Quantum Cryptography M Bisheh-Niasar, R Azarderakhsh, M Mozaffari 28th IEEE International Symposium on Computer Arithmetic (Arith 2021), Turin …, 2021 | 238 | 2021 |
| Blockchain technology in the future smart grids: A comprehensive review and frameworks A Hasankhani, SM Hakimi, M Bisheh-Niasar, M Shafie-khah, H Asadolahi International Journal of Electrical Power & Energy Systems 129, 106811, 2021 | 229 | 2021 |
| Cryptographic accelerators for digital signature based on Ed25519 M Bisheh-Niasar, R Azarderakhsh, M Mozaffari-Kermani IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29 (7 …, 2021 | 141 | 2021 |
| Instruction-Set Accelerated Implementation of CRYSTALS-Kyber M Bisheh-Niasar, R Azarderakhsh, M Mozaffari-Kermani IEEE Transactions on Circuits and Systems I: Regular Papers, 2021 | 126 | 2021 |
| Efficient Hardware Implementations for Elliptic Curve Cryptography over Curve448 M Bisheh-Niasar, R Azarderakhsh, MM Kermani International Conference on Cryptology in India, 228-247, 2020 | 96* | 2020 |
| Efficient and side-channel resistant Ed25519 on ARM Cortex-M4 D Owens, R El Khatib, M Bisheh-Niasar, R Azarderakhsh, MM Kermani IEEE Transactions on Circuits and Systems I: Regular Papers 71 (6), 2674-2686, 2024 | 50 | 2024 |
| Fast, small, and area-time efficient architectures for key-exchange on curve25519 M Bisheh-Niasar, R El Khatib, R Azarderakhsh, M Mozaffari-Kermani 2020 IEEE 27th Symposium on Computer Arithmetic (ARITH), 72-79, 2020 | 42 | 2020 |
| A monolithic hardware implementation of Kyber: Comparing apples to apples in PQC candidates M Bisheh-Niasar, R Azarderakhsh, M Mozaffari-Kermani International Conference on Cryptology and Information Security in Latin …, 2021 | 24 | 2021 |
| Compressed SIKE Round 3 on ARM Cortex-M4 M Anastasova, M Bisheh-Niasar, R Azarderakhsh, M Mozaffari 17th EAI International Conference on Security and Privacy in Communication …, 2021 | 22 | 2021 |
| Area-time efficient hardware architecture for signature based on Ed448 M Bisheh-Niasar, R Azarderakhsh, MM Kermani IEEE Transactions on Circuits and Systems II: Express Briefs 68 (8), 2942-2946, 2021 | 22 | 2021 |
| Efficient and side-channel resistant design of high-security Ed448 on ARM Cortex-M4 M Anastasova, M Bisheh-Niasar, H Seo, R Azarderakhsh, MM Kermani 2022 IEEE International Symposium on Hardware Oriented Security and Trust …, 2022 | 14 | 2022 |
| PQC Cloudization: Rapid Prototyping of Scalable NTT/INTT Architecture to Accelerate Kyber M Bisheh-Niasar, D Lo, A Parthasarathy, B Pelton, B Pillilli, B Kelly 2023 IEEE Physical Assurance and Inspection of Electronics (PAINE), 1-7, 2023 | 9 | 2023 |
| Side-channel analysis and countermeasure design for implementation of Curve448 on cortex-M4 M Bisheh-Niasar, M Anastasova, A Abdulgadir, H Seo, R Azarderakhsh Proceedings of the 11th International Workshop on Hardware and Architectural …, 2022 | 9 | 2022 |
| High level synthsis of cloud cryptography circuits MB Niasar, BS Pillilli US Patent App. 18/207,016, 2024 | 1 | 2024 |
| Montgomery multiplier architecture MB Niasar, BS Pillilli US Patent 12,500,736, 2025 | | 2025 |
| Cryptographic system real-time test vector leakage assessment MB Niasar, BS Pillilli US Patent 12,476,796, 2025 | | 2025 |
| Coefficient Rejection Sampling and Shuffling for Signature Generator MB Niasar, BS Pillilli, MJ NORRIS US Patent App. 18/657,460, 2025 | | 2025 |
| Lattice Based Cryptographic Rejection Bounded Sampling MB Niasar, BS Pillilli, MJ NORRIS US Patent App. 18/657,470, 2025 | | 2025 |
| Hash based cryptography accelerator MB Niasar, BS Pillilli US Patent 12,470,370, 2025 | | 2025 |
| Dilithium modular reduction architecture MB Niasar, NK UPADHYAYULA, BS Pillilli US Patent App. 18/647,426, 2025 | | 2025 |
Reza AzarderakhshProfessor at FAU and Founder of PQSecureVerified email at fau.edu
