| Parallel processing of matrix multiplication in a CPU and GPU heterogeneous environment S Ohshima, K Kise, T Katagiri, T Yuba International Conference on High Performance Computing for Computational …, 2006 | 85 | 2006 |
| Fiber: A generalized framework for auto-tuning software T Katagiri, K Kise, H Honda, T Yuba International Symposium on High Performance Computing, 146-159, 2003 | 84 | 2003 |
| A time-to-live based reservation algorithm on fully decentralized resource discovery in grid computing S Tangpongprasit, T Katagiri, K Kise, H Honda, T Yuba Parallel Computing 31 (6), 529-543, 2005 | 67 | 2005 |
| High-performance hardware merge sorter S Mashimo, T Van Chu, K Kise 2017 IEEE 25th Annual International Symposium on Field-Programmable Custom …, 2017 | 63 | 2017 |
| ABCLibScript: A directive to support specification of an auto-tuning facility for numerical software T Katagiri, K Kise, H Honda, T Yuba Parallel Computing 32 (1), 92-112, 2006 | 62 | 2006 |
| A high-performance and cost-effective hardware merge sorter without feedback datapath M Saitoh, EA Elsayed, T Van Chu, S Mashimo, K Kise 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom …, 2018 | 48 | 2018 |
| ABCLib_DRSSED: A parallel eigensolver with an auto-tuning facility T Katagiri, K Kise, H Honda, T Yuba Parallel Computing 32 (3), 231-250, 2006 | 42 | 2006 |
| Effect of auto-tuning with user's knowledge for numerical software T Katagiri, K Kise, H Honda, T Yuba Proceedings of the 1st conference on Computing frontiers, 12-25, 2004 | 40 | 2004 |
| Fast and cycle-accurate emulation of large-scale networks-on-chip using a single fpga TV Chu, S Sato, K Kise ACM Transactions on Reconfigurable Technology and Systems (TRETS) 10 (4), 1-27, 2017 | 32 | 2017 |
| Ultra-fast NoC emulation on a single FPGA T Van Chu, S Sato, K Kise 2015 25th International Conference on Field Programmable Logic and …, 2015 | 32 | 2015 |
| An exploration of state-of-the-art automation frameworks for FPGA-based DNN acceleration F Hamanaka, T Odan, K Kise, T Van Chu IEEE Access 11, 5701-5713, 2023 | 31 | 2023 |
| Solving the 24-queens Problem using MPI on a PC Cluster K Kise, T Katagiri, H Honda, T Yuba Graduate School of Information Systems, The University of Electro …, 2004 | 28 | 2004 |
| RVCoreP: An optimized RISC-V soft processor of five-stage pipelining H Miyazaki, T Kanamori, MA Islam, K Kise IEICE TRANSACTIONS on Information and Systems 103 (12), 2494-2503, 2020 | 25 | 2020 |
| A study of an infrastructure for research and development of many-core processors K Uehara, S Sato, T Miyoshi, K Kise 2009 International Conference on Parallel and Distributed Computing …, 2009 | 23 | 2009 |
| Outline of OROCHI: A Multiple Instruction Set Executable SMT Processor H Shimada, T Shimada, T Tabata, T Kitamura, T Kojima, Y Nakashima, ... Innovative architecture for future generation high-performance processors …, 2007 | 23 | 2007 |
| A cost-effective and scalable merge sorter tree on FPGAs T Usui, T Van Chu, K Kise 2016 Fourth International Symposium on Computing and Networking (CANDAR), 47-56, 2016 | 22 | 2016 |
| The synchronous vs. asynchronous NoC routers: an apple-to-apple comparison between synchronous and transition signaling asynchronous designs M Imai, T Van Chu, K Kise, T Yoneda 2016 Tenth IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 1-8, 2016 | 22 | 2016 |
| Very massive hardware merge sorter M Saitoh, K Kise 2018 International Conference on Field-Programmable Technology (FPT), 86-93, 2018 | 18 | 2018 |
| A high performance FPGA-based sorting accelerator with a data compression mechanism R Kobayashi, K Kise IEICE TRANSACTIONS on Information and Systems 100 (5), 1003-1015, 2017 | 18 | 2017 |
| OROCHI: A multiple instruction set SMT processor T Nakada, Y Nakashima, H Shimada, K Kise, T Kitamura Rainer Buchty, Jan-Philipp Weiß (eds.), 1, 2008 | 18 | 2008 |
