| Vega: A ten-core SoC for IoT endnodes with DNN acceleration and cognitive wake-up from MRAM-based state-retentive sleep mode D Rossi, F Conti, M Eggiman, A Di Mauro, G Tagliavini, S Mach, ... IEEE Journal of Solid-State Circuits 57 (1), 127-139, 2021 | 128 | 2021 |
| Quentin: an ultra-low-power pulpissimo soc in 22nm fdx PD Schiavone, D Rossi, A Pullini, A Di Mauro, F Conti, L Benini 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference …, 2018 | 124 | 2018 |
| Arnold: An eFPGA-augmented RISC-V SoC for flexible and low-power IoT end nodes PD Schiavone, D Rossi, A Di Mauro, FK Gürkaynak, T Saxe, M Wang, ... IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29 (4), 677-690, 2021 | 85 | 2021 |
| Mr. wolf: A 1 gflop/s energy-proportional parallel ultra low power soc for iot edge processing A Pullini, D Rossi, I Loi, A Di Mauro, L Benini ESSCIRC 2018-IEEE 44th European Solid State Circuits Conference (ESSCIRC …, 2018 | 79 | 2018 |
| 4.4 A 1.3 TOPS/W@ 32GOPS fully integrated 10-core SoC for IoT end-nodes with 1.7 μW cognitive wake-up from MRAM-based state-retentive sleep mode D Rossi, F Conti, M Eggiman, S Mach, A Di Mauro, M Guermandi, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 60-62, 2021 | 63 | 2021 |
| Always-on 674μ W@ 4GOP/s error resilient binary neural networks with aggressive SRAM voltage scaling on a 22-nm IoT end-node A Di Mauro, F Conti, PD Schiavone, D Rossi, L Benini IEEE Transactions on Circuits and Systems I: Regular Papers 67 (11), 3905-3918, 2020 | 53 | 2020 |
| Kraken: A direct event/frame-based multi-sensor fusion soc for ultra-efficient visual processing in nano-uavs A Di Mauro, M Scherer, D Rossi, L Benini arXiv preprint arXiv:2209.01065, 2022 | 44 | 2022 |
| Marsellus: A heterogeneous RISC-V AI-IoT end-node SoC with 2–8 b DNN acceleration and 30%-boost adaptive body biasing F Conti, G Paulin, A Garofalo, D Rossi, A Di Mauro, G Rutishauser, ... IEEE Journal of Solid-State Circuits 59 (1), 128-142, 2023 | 37 | 2023 |
| Dustin: A 16-cores parallel ultra-low-power cluster with 2b-to-32b fully flexible bit-precision and vector Lockstep execution mode G Ottavi, A Garofalo, G Tagliavini, F Conti, A Di Mauro, L Benini, D Rossi IEEE Transactions on Circuits and Systems I: Regular Papers 70 (6), 2450-2463, 2023 | 35 | 2023 |
| 22.1 A 12.4 TOPS/W@ 136GOPS AI-IoT system-on-chip with 16 RISC-V, 2-to-8b precision-scalable DNN acceleration and 30%-boost adaptive body biasing F Conti, D Rossi, G Paulin, A Garofalo, A Di Mauro, G Rutishauer, ... 2023 IEEE International Solid-State Circuits Conference (ISSCC), 21-23, 2023 | 35 | 2023 |
| An energy-efficient spiking neural network for finger velocity decoding for implantable brain-machine interface J Liao, L Widmer, X Wang, A Di Mauro, SR Nason-Tomaszewski, ... 2022 IEEE 4th International Conference on Artificial Intelligence Circuits …, 2022 | 33 | 2022 |
| Sne: an energy-proportional digital accelerator for sparse event-based convolutions A Di Mauro, AS Prasad, Z Huang, M Spallanzani, F Conti, L Benini 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 825-830, 2022 | 31 | 2022 |
| A 1.15 TOPS/W, 16-cores parallel ultra-low power cluster with 2b-to-32b fully flexible bit-precision and vector lockstep execution mode A Garofalo, G Ottavi, A Di Mauro, F Conti, G Tagliavini, L Benini, D Rossi ESSCIRC 2021-IEEE 47th European Solid State Circuits Conference (ESSCIRC …, 2021 | 27 | 2021 |
| Integrating event-based dynamic vision sensors with sparse hyperdimensional computing: A low-power accelerator with online learning capability M Hersche, EM Rella, A Di Mauro, L Benini, A Rahimi Proceedings of the ACM/IEEE International Symposium on Low Power Electronics …, 2020 | 27 | 2020 |
| Directly-trained spiking neural networks for deep reinforcement learning: Energy efficient implementation of event-based obstacle avoidance on a neuromorphic accelerator L Zanatta, A Di Mauro, F Barchi, A Bartolini, L Benini, A Acquaviva Neurocomputing 562, 126885, 2023 | 23 | 2023 |
| Siracusa: A 16 nm heterogenous risc-v soc for extended reality with at-mram neural engine AS Prasad, M Scherer, F Conti, D Rossi, A Di Mauro, M Eggimann, ... IEEE Journal of Solid-State Circuits 59 (7), 2055-2069, 2024 | 18 | 2024 |
| Colibriuav: An ultra-fast, energy-efficient neuromorphic edge processing uav-platform with event-based and frame-based cameras S Bian, L Schulthess, G Rutishauser, A Di Mauro, L Benini, M Magno arXiv preprint arXiv:2305.18371, 2023 | 17 | 2023 |
| Siracusa: A low-power on-sensor risc-v soc for extended reality visual processing in 16nm cmos M Scherer, M Eggimann, A Di Mauro, AS Prasad, F Conti, D Rossi, ... ESSCIRC 2023-IEEE 49th European Solid State Circuits Conference (ESSCIRC …, 2023 | 16 | 2023 |
| Colibries: A milliwatts risc-v based embedded system leveraging neuromorphic and neural networks hardware accelerators for low-latency closed-loop control applications G Rutishauser, R Hunziker, A Di Mauro, S Bian, L Benini, M Magno 2023 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2023 | 13 | 2023 |
| A 1036 TOp/s/W, 12.2 mW, 2.72 μJ/Inference All Digital TNN Accelerator in 22 nm FDX Technology for TinyML Applications M Scherer, A Di Mauro, G Rutishauser, T Fischer, L Benini 2022 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS), 1-3, 2022 | 13 | 2022 |
Luca BeniniETH Zürich, Università di BolognaVerified email at unibo.it
