| Run-time power estimation in high performance microprocessors R Joseph, M Martonosi Proceedings of the 2001 international symposium on Low power electronics and …, 2001 | 395 | 2001 |
| Understanding voltage variations in chip multiprocessors using a distributed power-delivery network MS Gupta, JL Oatley, R Joseph, GY Wei, DM Brooks 2007 Design, Automation & Test in Europe Conference & Exhibition, 1-6, 2007 | 276 | 2007 |
| Three-dimensional chip-multiprocessor run-time thermal management C Zhu, Z Gu, L Shang, RP Dick, R Joseph IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2008 | 241 | 2008 |
| Control techniques to eliminate voltage emergencies in high performance processors R Joseph, D Brooks, M Martonosi The Ninth International Symposium on High-Performance Computer Architecture …, 2003 | 205 | 2003 |
| Power, thermal, and reliability modeling in nanometer-scale microprocessors D Brooks, RP Dick, R Joseph, L Shang Ieee Micro 27 (3), 49-62, 2007 | 182 | 2007 |
| Multi-optimization power management for chip multiprocessors K Meng, R Joseph, RP Dick, L Shang Proceedings of the 17th international conference on Parallel architectures …, 2008 | 146 | 2008 |
| Reliability modeling and management of nanophotonic on-chip networks Z Li, M Mohamed, X Chen, E Dudley, K Meng, L Shang, AR Mickelson, ... IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20 (1), 98-111, 2010 | 111 | 2010 |
| Process variation aware cache leakage management K Meng, R Joseph Proceedings of the 2006 international symposium on Low power electronics and …, 2006 | 99 | 2006 |
| Identifying and predicting timing-critical instructions to boost timing speculation J Xin, R Joseph Proceedings of the 44th Annual IEEE/ACM International Symposium on …, 2011 | 66 | 2011 |
| Exploring circuit timing-aware language and compilation G Hoang, RB Findler, R Joseph Proceedings of the sixteenth international conference on Architectural …, 2011 | 54 | 2011 |
| Process variation characterization of chip-level multiprocessors L Zhang, LS Bai, RP Dick, L Shang, R Joseph Proceedings of the 46th Annual Design Automation Conference, 694-697, 2009 | 51 | 2009 |
| Live, runtime power measurements as a foundation for evaluating power/performance tradeoffs R Joseph, D Brooks, M Martonosi Workshop on Complexity Effectice Design WCED, held in conjunction with ISCA 28, 2001 | 49 | 2001 |
| A case for alternative nested paging models for virtualized systems G Hoang, C Bae, J Lange, L Zhang, P Dinda, R Joseph IEEE Computer Architecture Letters 9 (1), 17-20, 2010 | 42 | 2010 |
| Exploring salvage techniques for multi-core architectures R Joseph HPCRI-2005 Workshop in Conjunction with HPCA-2005, 2006 | 37 | 2006 |
| Wavelet analysis for microprocessor design: Experiences with wavelet-based dI/dt characterization R Joseph, Z Hu, M Martonosi 10th International Symposium on High Performance Computer Architecture (HPCA …, 2004 | 35 | 2004 |
| Modeling and characterizing power variability in multicore architectures K Meng, F Huebbers, R Joseph, Y Ismail 2007 IEEE International Symposium on Performance Analysis of Systems …, 2007 | 34 | 2007 |
| Ncpu: An embedded neural cpu architecture on resource-constrained low power devices for real-time end-to-end performance T Jia, Y Ju, R Joseph, J Gu 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture …, 2020 | 28 | 2020 |
| An instruction-driven adaptive clock management through dynamic phase scaling and compiler assistance for a low power microprocessor T Jia, R Joseph, J Gu IEEE Journal of Solid-State Circuits 54 (8), 2327-2338, 2019 | 18 | 2019 |
| Spectral analysis for characterizing program power and performance R Joseph, M Martonosi, Z Hu IEEE International Symposium on-ISPASS Performance Analysis of Systems and …, 2004 | 17 | 2004 |
| System and method for associative power and clock management with instruction governed operation for power efficient computing J Gu, R Joseph US Patent 10,705,589, 2020 | 14 | 2020 |
