| CC-SPRA: Correlation Coefficients Approach for Signal Probability-Based Reliability Analysis H Jahanirad IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2019 | 38 | 2019 |
| Broadband class-E power amplifier design using tunable output matching network F Moloudi, H Jahanirad AEU-International Journal of Electronics and Communications 118, 153142, 2020 | 30 | 2020 |
| FPGA-based implementation of deep neural network using stochastic computing M Nobari, H Jahanirad Applied Soft Computing 137, 110166, 2023 | 29 | 2023 |
| Hardware acceleration of YOLOv7-tiny using high-level synthesis tools A Hosseiny, H Jahanirad Journal of Real-Time Image Processing 20 (4), 75, 2023 | 27 | 2023 |
| Efficient reliability evaluation of combinational and sequential logic circuits H Jahanirad Journal of Computational Electronics, 1-13, 2019 | 24 | 2019 |
| NN-SSTA: A deep neural network approach for statistical static timing analysis MA Savari, H Jahanirad Expert Systems with Applications 149, 113309, 2020 | 23 | 2020 |
| BIST-based testing and diagnosis of LUTs in SRAM-based FPGAs H Jahanirad, H Karam Emerging Science Journal 1 (4), 216-225, 2017 | 21 | 2017 |
| Fast reliability analysis method for sequential logic circuits K Mohammadi, H Jahanirad, P Attarsharghi 2011 21st International Conference on Systems Engineering, 352-356, 2011 | 17 | 2011 |
| Deep transfer learning approach for digital circuits vulnerability analysis MM Rahimifar, H Jahanirad, M Fathi Expert Systems with Applications 237, 121757, 2024 | 12 | 2024 |
| Reliable Implementation on SRAM-based FPGA using Evolutionary Methods. H Jahanirad, K Mohammadi IETE Journal of Research (Taylor & Francis) 59 (5), 2013 | 11 | 2013 |
| SEQUENTIAL LOGIC CIRCUITS RELIABILITY ANALYSIS H Jahanirad, K Mohammadi Journal of Circuits, Systems, and Computers 21 (05), 1250040, 2012 | 10 | 2012 |
| An evolutionary approach to implement logic circuits on three dimensional FPGAs H Rahimi, H Jahanirad Expert Systems with Applications 174, 114780, 2021 | 9 | 2021 |
| Dynamic power-gating for leakage power reduction in FPGAs H Jahanirad Frontiers of Information Technology & Electronic Engineering 24 (4), 582-598, 2023 | 8 | 2023 |
| A concurrent BIST architecture for combinational logic circuits A Menbari, H Jahanirad 2020 10th International Conference on Computer and Knowledge Engineering …, 2020 | 8 | 2020 |
| Highly efficient implementation of chaotic systems utilizing high-level synthesis tools M Vaziri, H Jahanirad 2022 30th International Conference on Electrical Engineering (ICEE), 501-506, 2022 | 6 | 2022 |
| A low-cost BIST design supporting offline and online tests A Menbari, H Jahanirad Journal of Electronic Testing 38 (1), 107-123, 2022 | 6 | 2022 |
| An efficient reliability estimation method for CNTFET‐based logic circuits H Jahanirad, M Hosseini ETRI Journal, 2021 | 6 | 2021 |
| BIST-based online test approach for SRAM-based FPGAs H Jahanirad, H Karam Electrical Engineering (ICEE), Iranian Conference on, 178-183, 2018 | 6 | 2018 |
| Single fault reliability analysis in FPGA implemented circuits H Jahanirad, K Mohammadi, P Attarsharghi Thirteenth International Symposium on Quality Electronic Design (ISQED), 49-56, 2012 | 6 | 2012 |
| Low-Cost and hardware efficient implementation of pooling layers for stochastic CNN accelerators M Vaziri, H Jahanirad 2022 12th International Conference on Computer and Knowledge Engineering …, 2022 | 5 | 2022 |
Ahmad MenbariPhD student, Technische Universität IlmenauVerified email at tu-ilmenau.de
