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Joseph Melber
Joseph Melber
Verified email at amd.com
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A study of pointer-chasing performance on shared-memory processor-FPGA systems
G Weisz, J Melber, Y Wang, K Fleming, E Nurvitadhi, JC Hoe
Proceedings of the 2016 ACM/SIGDA International Symposium on Field …, 2016
542016
SPARTA: spatial acceleration for efficient and scalable horizontal diffusion weather stencil computation
G Singh, A Khodamoradi, K Denolf, J Lo, J Gómez-Luna, J Melber, ...
Proceedings of the 37th International Conference on Supercomputing, 463-476, 2023
242023
Efficiency, Expressivity, and Extensibility in a Close-to-Metal NPU Programming Interface
E Hunhoff, J Melber, K Denolf, A Bisca, S Bayliss, S Neuendorffer, J Fifield, ...
2025 IEEE 33rd Annual International Symposium on Field-Programmable Custom …, 2025
82025
A service-oriented memory architecture for FPGA computing
J Melber, JC Hoe
2020 30th International Conference on Field-Programmable Logic and …, 2020
52020
Exploiting the Common Case When Accelerating Input-Dependent Stream Processing by FPGA
Z Zhao, J Melber, S Sahay, S Obla, E Nurvitadhi, JC Hoe
IEEE Transactions on Computers 72 (5), 1343-1355, 2022
22022
From Loop Nests to Silicon: Mapping AI Workloads onto AMD NPUs with MLIR-AIR
E Wang, S Bayliss, A Bisca, Z Blair, S Chowdhary, K Denolf, J Fifield, ...
arXiv preprint arXiv:2510.14871, 2025
12025
Leveraging the IRON AI Engine API to program the Ryzen™ AI NPU
J Melber, K Denolf, A Schmidt, A Bisca, J Fifield, A Khodamoradi, ...
57th IEEE/ACM International Symposium on Microarchitecture (MICRO'24) Tutorial, 2024
12024
Fluid: Raising the Level of Abstraction for FPGA Accelerator Development without Compromising Performance
JG Melber
Carnegie Mellon University, 2021
12021
Dynamically pooled allocations of memory buffers on spatial compute architectures
K Denolf, A BISCA, J MELBER, A Khodamoradi, G Singh
US Patent App. 18/758,280, 2026
2026
Dynamic allocation of work and data on spatial compute architectures
J MELBER, A BISCA, K Denolf, G Singh, A Khodamoradi
US Patent App. 18/758,300, 2026
2026
Striking the Balance: GEMM Performance Optimization Across Generations of Ryzen AI NPUs
E Taka, A Roesti, J Melber, P Vasireddy, K Denolf, D Marculescu
arXiv preprint arXiv:2512.13282, 2025
2025
Can Asymmetric Tile Buffering Be Beneficial?
C Wang, W Pang, X Wu, G Jun, L Romero, E Taka, D Marculescu, ...
arXiv preprint arXiv:2511.16041, 2025
2025
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