| Large-scale power combining and mixed-signal linearizing architectures for watt-class mmWave CMOS power amplifiers R Bhat, A Chakrabarti, H Krishnaswamy IEEE Transactions on Microwave Theory and Techniques 63 (2), 703-718, 2015 | 63 | 2015 |
| Large-scale power-combining and linearization in watt-class mmWave CMOS power amplifiers R Bhat, A Chakrabarti, H Krishnaswamy 2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 283-286, 2013 | 58 | 2013 |
| A watt-level 2.4 GHz RF I/Q power DAC transmitter with integrated mixed-domain FIR filtering of quantization noise in 65 nm CMOS R Bhat, H Krishnaswamy 2014 IEEE Radio Frequency Integrated Circuits Symposium, 413-416, 2014 | 51 | 2014 |
| Wideband mixed-domain multi-tap finite-impulse response filtering of out-of-band noise floor in watt-class digital transmitters R Bhat, J Zhou, H Krishnaswamy IEEE Journal of Solid-State Circuits 52 (12), 3405-3420, 2017 | 36 | 2017 |
| A fully integrated 160Gb/s D-band transmitter with 1.1 pJ/b efficiency in 22nm FinFET technology S Callender, A Whitcombe, A Agrawal, R Bhat, M Rahman, CC Lee, ... 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 78-80, 2022 | 32 | 2022 |
| 13.10 A> 1W 2.2 GHz switched-capacitor digital power amplifier with wideband mixed-domain multi-tap FIR filtering of OOB noise floor R Bhat, J Zhou, H Krishnaswamy 2017 IEEE International Solid-State Circuits Conference (ISSCC), 234-235, 2017 | 27 | 2017 |
| A 128-Gb/s D-Band Receiver With Integrated PLL and ADC Achieving 1.95-pJ/b Efficiency in 22-nm FinFET A Agrawal, A Whitcombe, W Shin, R Bhat, S Kundu, P Sagazio, ... IEEE Journal of Solid-State Circuits 58 (12), 3364-3379, 2023 | 26 | 2023 |
| A fully integrated 160-Gb/s D-band transmitter achieving 1.1-pJ/b efficiency in 22-nm FinFET S Callender, A Agrawal, A Whitcombe, R Bhat, M Rahman, CC Lee, ... IEEE Journal of Solid-State Circuits 57 (12), 3582-3598, 2022 | 26 | 2022 |
| 18.2 A 128Gb/s 1.95 pJ/b D-Band Receiver with Integrated PLL and ADC in 22nm FinFET A Agrawal, A Whitcombe, W Shin, R Bhat, S Kundu, P Sagazio, ... 2023 IEEE International Solid-State Circuits Conference (ISSCC), 284-286, 2023 | 19 | 2023 |
| Design tradeoffs and predistortion of digital Cartesian RF-power-DAC transmitters R Bhat, H Krishnaswamy IEEE Transactions on Circuits and Systems II: Express Briefs 63 (11), 1039-1043, 2016 | 18 | 2016 |
| Real-time blocker-adaptive broadband wireless receiver for low-power operation under co-existence in 5G and beyond S Sen, R Bhat, Y Wang, S Pellerano, C Hull, F Sheikh US Patent 9,698,838, 2017 | 9 | 2017 |
| A compact fully integrated high-efficiency 5GHz stacked class-E PA in 65nm CMOS based on transformer-based charging acceleration J Chen, R Bhat, H Krishnaswamy 2012 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS), 1-4, 2012 | 8 | 2012 |
| Self-interference cancellation system and method R Bhat, S Pellerano, B Carlton US Patent 10,873,360, 2020 | 6 | 2020 |
| IEEE Trans. Microw. Theory Tech. R Bhat, A Chakrabarti, H Krishnaswamy IEEE Trans. Microw. Theory Tech 63 (2), 713-718, 2015 | 5 | 2015 |
| Communication device A Agrawal, S Callender, BR Carlton, CD Hull, S Pellerano, M Rahman, ... US Patent 12,212,351, 2025 | 2 | 2025 |
| Circuits for power-combined power amplifier arrays R Bhat, H Krishnaswamy US Patent 10,063,197, 2018 | 2 | 2018 |
| Adapting Pettigrew’s amplitude-locked loop for fast and synchronized extraction of fundamental and harmonics JM Gonda, RA Bhat, S David Proceedings of the Third International Conference on Power Electronics and …, 2010 | 1 | 2010 |
| Interstage matching network attenuator R Bhat, S Callender US Patent 12,512,808, 2025 | | 2025 |
| Cmos compatible matrix computing network Z Zhou, R Bhat, R Dorrance, S Sinha, H Wang, S Yamada, TY Yang US Patent App. 19/086,424, 2025 | | 2025 |
| Variable gain amplifier with complementarily switched neutralized differential pair R Bhat, S Callender, P Baumgartner US Patent App. 18/212,308, 2024 | | 2024 |
