| Memory performance and cache coherency effects on an intel nehalem multiprocessor system D Molka, D Hackenberg, R Schöne, MS Müller Parallel Architectures and Compilation Techniques, 2009. PACT'09. 18th …, 2009 | 361 | 2009 |
| An energy efficiency feature survey of the intel haswell processor D Hackenberg, R Schöne, T Ilsche, D Molka, J Schuchart, R Geyer 2015 IEEE international parallel and distributed processing symposium …, 2015 | 329 | 2015 |
| Power measurement techniques on standard compute nodes: A quantitative comparison D Hackenberg, T Ilsche, R Schöne, D Molka, M Schmidt, WE Nagel 2013 IEEE International Symposium on Performance Analysis of Systems and …, 2013 | 224 | 2013 |
| Comparing cache architectures and coherency protocols on x86-64 multicore SMP systems D Hackenberg, D Molka, WE Nagel Proceedings of the 42Nd Annual IEEE/ACM International Symposium on …, 2009 | 201 | 2009 |
| SPEC OMP2012—an application benchmark suite for parallel systems using OpenMP MS Müller, J Baron, WC Brantley, H Feng, D Hackenberg, R Henschel, ... OpenMP in a Heterogeneous World: 8th International Workshop on OpenMP, IWOMP …, 2012 | 118 | 2012 |
| Characterizing the energy consumption of data transfers and arithmetic operations on x86− 64 processors D Molka, D Hackenberg, R Schöne, MS Müller International conference on green computing, 123-133, 2010 | 108 | 2010 |
| Cache Coherence Protocol and Memory Performance of the Intel Haswell-EP Architecture D Molka, D Hackenberg, R Schöne, WE Nagel Parallel Processing (ICPP), 2015 44th International Conference on, 739-748, 2015 | 104 | 2015 |
| HDEEM: high definition energy efficiency monitoring D Hackenberg, T Ilsche, J Schuchart, R Schöne, WE Nagel, M Simon, ... Proceedings of the 2nd International Workshop on Energy Efficient …, 2014 | 98 | 2014 |
| Main memory and cache performance of intel sandy bridge and AMD bulldozer D Molka, D Hackenberg, R Schöne Proceedings of the workshop on Memory Systems Performance and Correctness, 4, 2014 | 95 | 2014 |
| Energy efficiency features of the Intel Skylake-SP processor and their impact on performance R Schöne, T Ilsche, M Bielert, A Gocht, D Hackenberg 2019 International Conference on High Performance Computing & Simulation …, 2019 | 82 | 2019 |
| Memory Performance at Reduced CPU Clock Speeds: An Analysis of Current x86 64 Processors R Schöne, D Hackenberg, D Molka Proceedings of the 2012 USENIX conference on Power-Aware Computing and …, 2012 | 71 | 2012 |
| Introducing FIRESTARTER: A processor stress test utility D Hackenberg, R Oldenburg, D Molka, R Schöne 2013 International Green Computing Conference Proceedings, 1-9, 2013 | 66 | 2013 |
| Energy Efficiency Aspects of the AMD Zen 2 Architecture R Schöne, T Ilsche, M Bielert, M Velten, M Schmidl, D Hackenberg 2021 IEEE International Conference on Cluster Computing (CLUSTER), 562-571, 2021 | 60 | 2021 |
| Detecting Memory-Boundedness with Hardware Performance Counters D Molka, R Schöne, D Hackenberg, WE Nagel Proceedings of the 8th ACM/SPEC on International Conference on Performance …, 2017 | 60 | 2017 |
| Comprehensive performance tracking with vampir 7 H Brunst, D Hackenberg, G Juckeland, H Rohling Tools for High Performance Computing 2009: Proceedings of the 3rd …, 2010 | 58 | 2010 |
| Memory Performance of AMD EPYC Rome and Intel Cascade Lake SP Server Processors M Velten, R Schöne, T Ilsche, D Hackenberg Proceedings of the 2022 ACM/SPEC on International Conference on Performance …, 2022 | 51 | 2022 |
| Power Measurements for Compute Nodes: Improving Sampling Rates, Granularity and Accuracy T Ilsche, D Hackenberg, S Graul, R Schöne, J Schuchart Sixth Int. Green and Sustainable Conputing Conference, 2015 | 50 | 2015 |
| The READEX formalism for automatic tuning for energy efficiency J Schuchart, M Gerndt, PG Kjeldsberg, M Lysaght, D Horák, L Říha, ... Computing, 1-19, 2017 | 44 | 2017 |
| The vampirtrace plugin counter interface: introduction and examples R Schöne, R Tschüter, T Ilsche, D Hackenberg Euro-Par 2010 Parallel Processing Workshops: HeteroPar, HPCC, HiBB, CoreGrid …, 2011 | 41 | 2011 |
| Fast matrix multiplication on Cell (SMP) systems D Hackenberg ZIH, TU Dresden, 2007 | 36* | 2007 |
Robert SchöneFaculty Computer Science / ZIH, TU DresdenVerified email at tu-dresden.de
